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ADSP-2192 Peripheral Device Control Registers
PCI Configuration Register Space, Function 1
PCI Configuration Spaces should be accessed only by the DSP, and only
during the boot process. After the PCI interface has been configured, bit 2
PCI_CFGCTL
of the
the PCI interface access to these registers while at the same time denying
the DSP access.
Access to these registers is controlled by the PCI RDY bit in the
Chip Mode/Status Register (Page 0x00, Address 0x00). See
"ADSP-2192 Chip Control Registers" on page
Table B-26. Function 1 Registers
Register Name
PCI_CFG1_VID
PCI_CFG1_DID
PCI_CFG1_CCODEL
PCI_CFG1_CCODEH
PCI_CFG1_SVID
PCI_CFG1_SDID
B-58
ADSP-219x/2192 DSP Hardware Reference
ConfRdy
register (
) should be set by the DSP. This allows
Description
PCI
Address
Config1 Vendor
0x01-0x00
ID
Config1 Device
0x03-0x02
ID
Config1 Class
0x08
Code[7:0], Rev
ID
Config1 Class
0x0B-0x0A
Code[23:8]
Config1 Sub-
0x2D-0x2C
system Vendor
ID
Config1 Sub-
0x2F-0x2E
system Device ID
B-13.
USB
DSP
Address
I/O
Page
n/a
0x0A
n/a
0x0A
n/a
0x0A
n/a
0x0A
n/a
0x0A
n/a
0x0A
DSP
I/O
Address
0x00
0x02
0x08
0x0A
0x2C
0x2E
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