Analog Devices ADSP-219 Series Hardware Reference Manual page 21

Table B-6. DSP Interrupt/Powerdown (PWRPx) Register Bit Descriptions
(Continued)
Bit Position Bit Name
2 RSTD
3 FIEN
4 PMWE
5 AWE
6 GWE
7 RWE
8 PMIEN
ADSP-2192 DSP Peripheral Registers
Description
DSP Soft Reset
When written to a 1, causes a soft reset to this DSP. Retains a
1 until cleared by writing to a 0.
If the DSP core is powered down, it must be powered up first
(DSP:PU bit written to 1) before resetting.
DSP Interrupt Enable: AC'97 Frame
When 1, enables an AC'97 Frame interrupt (IMASK bit 15) to
this DSP from the AC'97 Interface. If 0, no interrupt is
signalled (Read/Write). The actual interrupt occurs once per
AC'97 Frame, at the second bit of Slot 12.
Power Management Wakeup Enable.
When 1, enables waking the respective DSP on a Power Man-
agement State Change event (Read/Write).
DSP Wakeup Enable: GPIO Interrupt, AC'97 Interrupt.
When 1, enables this DSP to wake from powerdown upon an
event from the indicated source. (Read/Write).
DSP Wakeup Enable: GPIO Interrupt, AC'97 Interrupt.
When 1, enables this DSP to wake from powerdown upon an
event from the indicated source. (Read/Write).
DSP Wakeup Enable: GPIO Interrupt, AC'97 Interrupt.
When 1, enables this DSP to wake from powerdown upon an
event from the indicated source. (Read/Write).
Power Management Interrupt Enable.
When 1, enables interrupting the respective DSP on a Power
Management State Change event. (The interrupt level is the
same as used for GPIO and AC'97 interrupt) (Read / Write).
ADSP-219x/2192 DSP Hardware Reference B-21