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Table B-5. Bit Descriptions for PWRCFG0, PWRCFG1, and PWRCFG2
Registers (Continued)
Bit Position
Bit Name
14
SPME
15
PME
DSP Powerdown (PWRPx) Registers
These two registers share the following bit layout. One register corre-
sponds to each DSP.
All bits in this register reset to zero.
15
14
13
12
ADSP-2192 DSP Peripheral Registers
Description
Power Management Event (Set).
A write of 1 to this bit sets the PME bit for this
function. A write of 0 has no effect. Always
reads 0.
Power Management Event (Status/Clear).
1=
A power management event has been detected for this
function. This is an alias of the PME bit in the Power
Management Control/Status Register in PCI Configura-
tion Space for this function. A write of 1 to this bit
clears PME.
0=
A write of 0 has no effect.
11
10
9
8
ADSP-219x/2192 DSP Hardware Reference
7
6
5
4
3
2
1
0
B-19
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