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ADSP-2192 Peripheral Device Control Registers
Power Management Functions
Power management registers share the same bit specifications. Each regis-
ter corresponds to one of the PCI functions:
15
14
All bits in this register reset to zero.
Table B-5. Bit Descriptions for PWRCFG0, PWRCFG1, and PWRCFG2
Registers
Bit Position
Bit Name
1:0
PWRST<1:0>
4:2
Reserved
5
APME
6
GPME
7
Reserved
8
PME_EN
13:9
Reserved
B-18
ADSP-219x/2192 DSP Hardware Reference
13:9
8
Description
PCI Function Power State.
Reports this function's PCI Power Management state from its
PMCSR register in PCI Configuration Space. (Read Only)
AC'97 Power Management Event Enable.
Enables setting this function's PME bit upon
1=
an AC'97 interrupt/wake event. (Read/Write)
GPIO Power Management Event Enable.
Enables setting this function's PME bit upon a
1=
GPIO Wakeup event. (Read/Write)
Reserved
Power Management Event Enable.
PME_EN bit is set in this function's PMCSR
1=
register in PCI Configuration space.
7
6
5
4
3
2
1
0
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