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ADSP-2192 Peripheral Device Control Registers
Table B-22. PCI_DMACx Register Bit Descriptions (Continued)
Bit
Bit name
position
8
EMPTY
9
HALT
10
LOOP
15:11
Reserved
PCI Interrupt (PCI_IRQSTAT) Register
There are a variety of potential sources of interrupts to the PCI host
besides the bus master DMA interrupts. A single interrupt pin,
nals these interrupts back to the host. The PCI Interrupt Register
consolidates all of the possible interrupt sources; the bits of this register
are shown in
Table B-28 on page
ious sources and can be cleared by writing a 1 to the bits to be cleared.
Interrupts may be sensitive either to edges or levels, as indicated in
Table
B-28. In particular, the PCI GPIO interrupt is level sensitive, and is
asserted when any of the GPIO's individual sticky status bits is true. If an
interrupt service routine is in the process of acknowledging one GPIO
interrupt (by clearing its sticky status and then writing a 1 to
PCI_IRQSTAT:GPIO
the ISR to miss the second event, should it occur between the time the
ISR reads the GPIOs' status and when the ISR clears the
bit. The GPIO interrupt is level sensitive to accommodate this case; the
PCI_IRQSTAT:GPIO
clearing. The ISR may be written in two ways to detect this case: it may
either exit and be immediately re-triggered, or it may read back the
PCI_IRQSTAT
register after the clear to see if any bit has been set again indi-
cating the occurrence of some new interrupt.
Status bits for all possible PCI interrupt sources (read/write-1-clear).
B-50
ADSP-219x/2192 DSP Hardware Reference
Description
DMA FIFO Empty Status (1 = Empty).
DMA Channel Halt Status (1 = Halted).
DMA Channel Loop Status (1 = Looping Occurred).
) while an event occurs on another GPIO, it is possible for
interrupt bit and the
B-60. The register bits are set by the var-
INTA
pin immediately reassert after
INTA
, is sig-
PCI_IRQSTAT:GPIO
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