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10.5.2.1 Diagnostic Features
The signals that will be routed into PPDA through P1 for diagnostics include:
•
An electronic ID is used to identify the board type, revision, and serial number.
•
There are two analog dc voltage feedbacks. One is used for the positive bus with respect to earth, and one is used for the
negative bus with respect to earth (2 analogs). PPDA uses these signals to create two signals with DC_24VFdbkMag
indicating total magnitude (difference between positive and negative) and DC_24VGnd_FdbkMag indicating voltage
offset for a system ground. Voltage feedback accuracy is specified at ±1% of 48 V and exceeds ±0.25% of 48 V or ±0.12
V.
•
Each fused output drives an optocoupler circuit. The optocouplers are combined into two multiplexed fuse indications
(multiplexed on two analog signals). They yield six Boolean values after PPDA decodes the signal.
•
Test points HW1 and HW2 provide impedance limited connections to the positive and negative dc power for voltage
measurements.
•
Two dc power converter output status dry contact indications (multiplexed on one analog) yield two Boolean values after
PPDA decodes the signal. These may be used to identify that one of two redundant power supplies has failed and requires
attention.
Other core PDM board feedback may pass through JPDE using the P2 connector.
10.5.2.2 JPDE Grounding
Mark VIeS control systems separate ground into a functional earth (FE) and a protective earth (PE). The protective earth is
intended for power distribution functions such as JPDE, while functional earth is used for quiet uses such as the control
electronics and field signals.
Grounding of the JPDE takes place through metal mounting standoffs. The ground is applied to the metal switch bodies on
JPDE. In addition, the ground is used as a local reference when creating the magnitude feedback signals appearing on P2.
10.5.2.3 JPDE Physical Arrangement
JPDE is designed to accept power input from the right hand side and deliver power output from the left hand side. The P1 and
P2 ribbon cable headers on all of the JPDx boards are designed so the JPDS holding the PPDA I/O pack is best located at the
top of the arrangement. This allows ribbon cables to flow from one to the next, exiting the top and entering the bottom of the
next until the PPDA host is reached.
10.5.2.4 PPDA Configuration for JPDE Feedback
An alarm is generated if the value of DC_24V FdbkMag drops below the voltage specified by DC_24v_Trig_Volt. The value
of DC_24 V_Trig_Volt should be coordinated with the application voltage and expectations for voltage regulation. An alarm is
generated if the value of DC_24VGnd_FdbkMag exceeds the voltage specified by Gnd_Mag_Trig_Volt. This sets up the
sensitivity of the ground fault detection. To disable fuse monitoring in the three switched output circuits, change the FuseDiag
from the default Enable to Disable. These setting changes are needed for battery-powered applications.
10.5.3 Installation
The JPDE board is compatible with the feedback signal P1/P2 connectors on JPDS and JPDG leading to a PPDA I/O pack.
The JPDE is base-mounted vertically on a metal bracket in a cabinet used by the PDM. Refer to the wiring diagrams for
power input and output routing. There is a 50-pin diagnostic connector mounted on the top and bottom of the board.
10.5.3.1 Grounding
The JPDE board is grounded through the sheet metal bracket to the underlying back base. In most cases, this is the system FE.
PDM Power Distribution Modules
Public Information
GEH-6855_Vol_II System Guide 367
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