Pci Express* X1 Port3; Jtag Headers; Jtag Chain On The Com Express* Module; Jtag Chain Jumper Options On The Com Express* Module - Intel Atom E660 User Manual

Reference Board Summary
4.6.4

PCI Express* x1 Port3

The PCI Express* port 3 link can connect to either two end points via a signal switch
(Pericom PI2PCIE212-D*). The first target device is a x4 PCIe* slot (X10); the second
target device is a PCI Express* Mini Card connector (X8).
This PCIe* signal switch is controlled by slide switch (SW4 - bit 1), see
Figure 14
4.7

JTAG Headers

The JTAG headers are used primarily for the microcontroller firmware upgrade and
boundary scan testing.
The Intel
port (J1A1) on the COM Express* module. Jumper (J1B1) allows you to bypass the CPU
or I/O chain, see
Table 18.

JTAG Chain Jumper Options on the COM Express* Module

CPU JTAG only (default)
The System Management CPLD can be accessed in-system via the JTAG header (J5D5)
on the COM Express* module.
Module.
Figure 16.

JTAG Chain on the COM Express* Module

January 2012
Document Number: 324213-002
and Table 14.
®
Atom™ Processor E660 JTAG chains are daisy chained onto the XDP JTAG
Figure 13.
JTAG Chain
CPU and I/O JTAG
I/O JTAG only
Figure 16
®
Intel Atom™ Processor E660 with Intel
J1B1 Options
1-2, 3-4, 5-6
1-2, 4-6
1-3, 5-6
shows the JTAG chain on the COM Express*
®
Platform Controller Hub EG20T Development Kit
Figure 3,
User Manual
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