Features; Figure 20. Spi Point-To-Point Single-Ended Topology; Table 11. Spi Platform Routing Guidelines - Intel Quark D2000 Design Manual

SPI

Figure 20. SPI Point-to-Point Single-Ended Topology

Table 11. SPI Platform Routing Guidelines

(SDIN, SDOUT, SCLK, SCS)
Transmission Line
Segment
Routing Layer
(Microstrip/Stripline)
Characteristic Impedance
Trace Width (w)
Trace Spacing (S): Between
SPI signals
Trace Spacing (S2):
Between SPI signals and
other signals
Trace Length
Trace Total Length
7.1

Features

The following is a list of the SPI master features:
 One SPI master interface

Control of up to 4 Slave Selects
 Frame formats:
 Motorola* SPI
 Texas Instruments* SSP
 National Semiconductor Microwire*

Transfer modes:
 Transmit & Receive
November 2016
Document Number: 333580-002EN
SPI_S
BRK OUT
50Ω + 10% (MS)
50Ω + 10% (SL)
Meet impedance
5 mil minimum
5 mil minimum
0.5" max
SPI Slave
Main
L1 L2
MS/SL MS/SL
50Ω + 10% (MS)
50Ω + 10% (SL)
Meet impedance
2*w
3*w
7" max
Total trace length = 8" max
Intel® Quark™ Microcontroller D2000
BRK IN
L3
MS/SL
50Ω + 10% (MS)
50Ω + 10% (SL)
Meet impedance
5 mil minimum
5 mil minimum
0.5" max
Platform Design Guide
31