10/100/1000 Ethernet Phy - Intel Stratix 10 GX FPGA User Manual

Receive bus
B58
B62
B66
B70
B74
B78
B11

4.6.2. 10/100/1000 Ethernet PHY

Figure 9.
Table 17.
Board Reference
(U13)
23
25
24
28
76
74
® ®
Intel Stratix
30
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Schematic Signal
Name
PCIE_RX_P10
PCIE_RX_P11
PCIE_RX_P12
PCIE_RX_P13
PCIE_RX_P14
PCIE_RX_P15
PCIE_WAKEn_R
The Intel Stratix 10 GX FPGA development board supports 10/100/1000 base-T
Ethernet using an external Marvell 88E1111 PHY and Intel Triple-Speed Ethernet Intel
FPGA IP core MAC function. The PHY-to-MAC interface employs SGMII using the Intel
Stratix 10 GX FPGA LVDS pins in Soft-CDR mode at 1.25 Gbps transmit and receive.
In 10 Mb or 100 Mb mode, the SGMII interface still runs at 1.25 GHz but the packet
data is repeated 10 or 100 times. The MAC function must be provided in the FPGA for
typical networking applications.
The Marvell 88E1111 PHY uses a 2.5V and 1.0V power rails and requires a 25 MHz
reference clock driven from a dedicated oscillator. The PHY interfaces to a HALO
HFJ11-1G02E model RJ45 with internal magnetics that can be used for driving copper
lines with Ethernet traffic.
SGMII Interface between FPGA (MAC) and Marvell 88E1111 PHY
MDI Interface
RJ45+
Magnetics
Ethernet PHY Pin Assignments, Signal Names and Functions
Schematic Signal
Name
ENET_INTn
ENET_MDC
ENET_MDIO
ENET_RESETn
ENET_LED_LINK10
ENET_LED_LINK100
10 GX FPGA Development Kit User Guide
FPGA Pin Number I/O Standard
AU43 1.4 V PCML
AV45 1.4 V PCML
AR43 1.4 V PCML
AT45 1.4 V PCML
AP45 1.4 V PCML
AN43 1.4 V PCML
AU34 1.8V
SGMII TX/RX
Marvell 10/100/1000
PHY
FPGA Pin Number I/O Standard
AC35 3.0V
AD35 3.0V
AD34 3.0V
AB34 3.0V
– 2.5V
– 2.5V
4. Board Components
UG-20046 | 2020.04.02
Description
Receive bus
Receive bus
Receive bus
Receive bus
Receive bus
Receive bus
Wake Signal
Intel
Stratix 10 FPGA
Description
Management bus
interrupt
Management bus data
clock
Management bus data
Device reset
10 Mb link LED
100 Mb LED
continued...
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