Xilinx Virtex-7 VC7203 User Manual page 23

X-Ref Target - Figure 1-11
Information for each GTX transceiver pin is shown in
Table 1-13: GTX Transceiver Pins
VC7203 GTX Transceiver Characterization Board
UG957 (v1.3) October 17, 2014
A
GTX Connector Pad
Figure 1-11: A – GTX Connector Pad. B – GTX Connector Pinout
U1 FPGA Pin Net Name
BB4 111_TX0_P
BB3 111_TX0_N
BB8 111_RX0_P
BB7 111_RX0_N
BA2 111_TX1_P
BA1 111_TX1_N
BA6 111_RX1_P
BA5 111_RX1_N
AY4 111_TX2_P
AY3 111_TX2_N
AY8 111_RX2_P
AY7 111_RX2_N
AW2 111_TX3_P
AW1 111_TX3_N
AW6 111_RX3_P
AW5 111_RX3_N
AV4 112_TX0_P
AV3 112_TX0_N
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Detailed Description
B
GTX
N
P N
N
P N
N
P N
N
P N
N
P N
GTX Connector Pinout
UG957_c1_11_100712
Table 1-13.
Quad Connector
111 J84
111 J84
111 J84
111 J84
111 J84
111 J84
111 J84
111 J84
111 J84
111 J84
111 J84
111 J84
111 J84
111 J84
111 J84
111 J84
112 J85
112 J85
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P
P
P
P
P
Trace Length
(mils)
1,929
1,929
2,149
2,148
1,808
1,808
1,855
1,855
2,097
2,097
2,101
2,100
2,650
2,650
2,533
2,532
2,692
2,692
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