Usb-To-Uart Bridge - Xilinx Virtex-7 VC7203 User Manual

Table 1-14:

USB-to-UART Bridge

Callout 21,
A USB-to-UART bridge (U34, Silicon Laboratories CP2103) is provided for serial
communication between a host computer and the FPGA over a USB cable. The USB
connector on the board is a mini-B receptacle (J79) and its pinout is shown in
Table 1-15: USB Mini-B Receptacle Pin Assignments and Signals
J79 Pin
The CP2103 supports an I/O voltage range of 1.8V to 3.3V. Xilinx UART IP is expected to
be implemented in the FPGA fabric. The FPGA supports the USB-to-UART bridge using
four signal pins:
•
•
•
•
Connections of these signals between the FPGA and the CP2103 are listed in
Table 1-16: FPGA to UART Connections
FPGA (U1)
Pin Function
B31 RTS
C31 CTS
A30 TX
A29 RX
VC7203 GTX Transceiver Characterization Board
UG957 (v1.3) October 17, 2014
GTX Transceiver Reference Clock Inputs (Cont'd)
U1 FPGA Pin Net Name
A10 119_REFCLK0_P
A9 119_REFCLK0_N
C10 119_REFCLK1_P
C9 119_REFCLK1_N
Figure 1-2.
Signal Name
+5V into the CP2103 USB-to-UART bridge at U34.
1 VBUS
Used to sense USB network connection.
2 USB_DATA_N Bidirectional differential serial data (N-side).
3 USB_DATA_P Bidirectional differential serial data (P-side).
4 GROUND Signal ground.
Transmit (TX)
Receive (RX)
Request to Send (RTS)
Clear to Send (CTS)
Direction I/O Standard
Output LVCMOS18
Input LVCMOS18
Output LVCMOS18
Input LVCMOS18
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Quad
119
119
119
119
Description
Schematic Net
Name
Pin
USB_CTS_I_B 22
USB_RTS_0_B 23
USB_RXD_I 24
USB_TXD_0 25
Detailed Description
Connector
J163
J163
J163
J163
Table 1-15.
Table 1-16.
Device (U34)
Function Direction
CTS Input
RTS Output
RXD Input
TXD Output
29
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