Superclock-2 Module - Xilinx Virtex-7 VC7203 User Manual

SuperClock-2 Module

Callout 10,
The SuperClock-2 module connects to the clock module interface connector (J82) and
provides a programmable, low-noise and low-jitter clock source for the VC7203 board. The
clock module maps to FPGA I/O by way of 24 control pins, 3 LVDS pairs, 1 regional clock
pair, and 1 reset pin.
interface. The VC7203 board also supplies UTIL_5V0, UTIL_3V3, UTIL_2V5 and
VCCO_HR input power to the clock module interface.
Table 1-9: SuperClock-2 FPGA I/O Mapping
FPGA (U1)
Pin Function
E12 Clock Recovery
D12 Clock Recovery
L12 Clock Recovery
L11 Clock Recovery
BA1 Clock Recovery
BB1 Clock Recovery
K19 Regional Clock
J18 Regional Clock
C19 Control I/O
B19 Control I/O
A16 Control I/O
A15 Control I/O
A20 Control I/O
A19 Control I/O
B17 Control I/O
A17 Control I/O
B21 Control I/O
A21 Control I/O
C18 Control I/O
B18 Control I/O
D20 Control I/O
C20 Control I/O
F17 Control I/O
E17 Control I/O
D21 Control I/O
VC7203 GTX Transceiver Characterization Board
UG957 (v1.3) October 17, 2014
Figure 1-2.
Table 1-9 shows the FPGA I/O mapping for the SuperClock-2 module
Direction I/O Standard
Input LVDS_25
Input LVDS_25
Input LVDS_25
Input LVDS_25
Output LVDS
Output LVDS
Input LVDS_25
Input LVDS_25
In/Out LVCMOS18
In/Out LVCMOS18
In/Out LVCMOS18
Output LVCMOS18
Output LVCMOS18
Output LVCMOS18
In/Out LVCMOS18
In/Out LVCMOS18
In/Out LVCMOS18
In/Out LVCMOS18
Output LVCMOS18
Output LVCMOS18
Output LVCMOS18
Output LVCMOS18
Output LVCMOS18
Output LVCMOS18
In/Out LVCMOS18
www.xilinx.com
Schematic
Net Name
Pin
CM_LVDS1_P 1
CM_LVDS1_N 3
CM_LVDS2_P 9
CM_LVDS2_N 11
CM_LVDS3_P 17
CM_LVDS3_N 19
CM_GCLK_P 25
CM_GCLK_N 27
CM_CTRL_0 61
CM_CTRL_1 63
CM_CTRL_2 65
CM_CTRL_3 67
CM_CTRL_4 69
CM_CTRL_5 71
CM_CTRL_6 73
CM_CTRL_7 75
CM_CTRL_8 77
CM_CTRL_9 79
CM_CTRL_10 81
CM_CTRL_11 83
CM_CTRL_12 85
CM_CTRL_13 87
CM_CTRL_14 89
CM_CTRL_15 91
CM_CTRL_16 93
Detailed Description
J82 Pin
Function Direction
Clock Recovery Output
Clock Recovery Output
Clock Recovery Output
Clock Recovery Output
Clock Recovery Input
Clock Recovery Input
Global Clock Output
Global Clock Output
NC —
NC —
NC —
DEC Input
INC Input
ALIGN Input
NC —
NC —
NC —
LOL
INT_ALRM Input
C1B Input
C2B Input
C3B Input
C1A Input
C2A Input
NC —
Send Feedback
19