User Pushbuttons (Active-High) - Xilinx Virtex-7 VC7203 User Manual

Table 1-11: User DIP Switches
Pin Function
E42 User Switch
C40 User Switch
C41 User Switch
H40 User Switch
H41 User Switch
H39 User Switch
G39 User Switch
G41 User Switch
Figure 1-9
X-Ref Target - Figure 1-9

User Pushbuttons (Active-High)

Callout 24,
SW4 and SW5 are active-High user pushbuttons that are connected to user I/O pins on the
FPGA as shown in
the user.
Table 1-12: User Pushbuttons
Pin Function
P41 User Pushbutton
N41 User Pushbutton
VC7203 GTX Transceiver Characterization Board
UG957 (v1.3) October 17, 2014
FPGA (U1)
Direction I/O Standard
Input LVCMOS18
Input LVCMOS18
Input LVCMOS18
Input LVCMOS18
Input LVCMOS18
Input LVCMOS18
Input LVCMOS18
Input LVCMOS18
shows the user test I/O connector J125 (callout 26,
Figure 1-2.
Table 1-12. These switches can be used for any purpose determined by
FPGA (U1)
Direction
Input
Input
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Schematic Net
Name
USER_SW1
USER_SW2
USER_SW3
USER_SW4
USER_SW5
USER_SW6
USER_SW7
USER_SW8
J125
1 2 USER_SW1
3 4 USER_SW2
5 6
USER_SW3
7 8 USER_SW4
9 10 USER_SW5
11 12 USER_SW6
GND
UG932_C1_09_100712
Figure 1-9: User Test I/O
Schematic Net
I/O Standard
LVCMOS18
LVCMOS18
Detailed Description
SW2 DIP J125 Test
Switch Pin Header Pin
1 2
2 4
3 6
4 8
5 10
6 12
7 —
8 —
Figure 1-2).
Reference
Name Designator
USER_PB1 SW5
USER_PB2 SW4
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