Xilinx Virtex-7 VC7203 User Manual page 56

Appendix C: Master Constraints File Listing
56
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set_property PACKAGE_PIN AA34 [get_ports FMC1_HB11_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HB11_P]
set_property PACKAGE_PIN AA35 [get_ports FMC1_HB11_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HB11_N]
set_property PACKAGE_PIN AE32 [get_ports FMC1_HB12_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HB12_P]
set_property PACKAGE_PIN AE33 [get_ports FMC1_HB12_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HB12_N]
set_property PACKAGE_PIN AF31 [get_ports FMC1_HB13_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HB13_P]
set_property PACKAGE_PIN AF32 [get_ports FMC1_HB13_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HB13_N]
set_property PACKAGE_PIN AE34 [get_ports FMC1_HB14_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HB14_P]
set_property PACKAGE_PIN AE35 [get_ports FMC1_HB14_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HB14_N]
set_property PACKAGE_PIN AE29 [get_ports FMC1_HB15_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HB15_P]
set_property PACKAGE_PIN AE30 [get_ports FMC1_HB15_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HB15_N]
set_property PACKAGE_PIN Y32 [get_ports FMC1_HB16_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HB16_P]
set_property PACKAGE_PIN Y33 [get_ports FMC1_HB16_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HB16_N]
#FMC2
set_property PACKAGE_PIN G31 [get_ports FMC2_PRSNT_M2C_L]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_PRSNT_M2C_L]
set_property PACKAGE_PIN E34 [get_ports FMC2_CLK0_M2C_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_CLK0_M2C_P]
set_property PACKAGE_PIN E35 [get_ports FMC2_CLK0_M2C_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_CLK0_M2C_N]
set_property PACKAGE_PIN D37 [get_ports FMC2_CLK1_M2C_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_CLK1_M2C_P]
set_property PACKAGE_PIN D38 [get_ports FMC2_CLK1_M2C_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_CLK1_M2C_N]
set_property PACKAGE_PIN M24 [get_ports FMC2_CLK2_BIDIR_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_CLK2_BIDIR_P]
set_property PACKAGE_PIN L24 [get_ports FMC2_CLK2_BIDIR_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_CLK2_BIDIR_N]
set_property PACKAGE_PIN K23 [get_ports FMC2_CLK3_BIDIR_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_CLK3_BIDIR_P]
set_property PACKAGE_PIN J23 [get_ports FMC2_CLK3_BIDIR_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_CLK3_BIDIR_N]
#FMC2 LA
set_property PACKAGE_PIN L31 [get_ports FMC2_LA00_CC_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_LA00_CC_P]
set_property PACKAGE_PIN K32 [get_ports FMC2_LA00_CC_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_LA00_CC_N]
set_property PACKAGE_PIN M32 [get_ports FMC2_LA01_CC_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_LA01_CC_P]
set_property PACKAGE_PIN L32 [get_ports FMC2_LA01_CC_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_LA01_CC_N]
set_property PACKAGE_PIN K35 [get_ports FMC2_LA02_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_LA02_P]
set_property PACKAGE_PIN J35 [get_ports FMC2_LA02_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_LA02_N]
set_property PACKAGE_PIN J32 [get_ports FMC2_LA03_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC2_LA03_P]
set_property PACKAGE_PIN J33 [get_ports FMC2_LA03_N]
www.xilinx.com VC7203 GTX Transceiver Characterization Board
UG957 (v1.3) October 17, 2014