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Master Constraints File Listing
The master Xilinx design constraints (XDC) file template for the VC7203 board provides
for designs targeting the VC7203 Virtex®-7 FPGA GTX Transceiver Characterization
Board. Net names in the listed constraints correlate with net names on the VC7203 board
schematic. Users must identify the appropriate pins and replace the net names below with
net names in the user RTL. See Vivado Design Suite User Guide: Using Constraints (UG903)
[Ref 5]
Note:
VC7203 Board XDC Listing
VC7203 GTX Transceiver Characterization Board
UG957 (v1.3) October 17, 2014
for more information.
Visit the
Virtex-7 FPGA VC7203 Characterization Kit support page
#FMC1
set_property PACKAGE_PIN AM38 [get_ports FMC1_PRSNT_M2C_L]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_PRSNT_M2C_L]
set_property PACKAGE_PIN AJ32 [get_ports FMC1_CLK0_M2C_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_CLK0_M2C_P]
set_property PACKAGE_PIN AK32 [get_ports FMC1_CLK0_M2C_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_CLK0_M2C_N]
set_property PACKAGE_PIN AL31 [get_ports FMC1_CLK1_M2C_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_CLK1_M2C_P]
set_property PACKAGE_PIN AL32 [get_ports FMC1_CLK1_M2C_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_CLK1_M2C_N]
set_property PACKAGE_PIN AD32 [get_ports FMC1_CLK2_BIDIR_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_CLK2_BIDIR_P]
set_property PACKAGE_PIN AD33 [get_ports FMC1_CLK2_BIDIR_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_CLK2_BIDIR_N]
set_property PACKAGE_PIN AC34 [get_ports FMC1_CLK3_BIDIR_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_CLK3_BIDIR_P]
set_property PACKAGE_PIN AD35 [get_ports FMC1_CLK3_BIDIR_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_CLK3_BIDIR_N]
#FMC1 LA
set_property PACKAGE_PIN AU38 [get_ports FMC1_LA00_CC_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_LA00_CC_P]
set_property PACKAGE_PIN AV38 [get_ports FMC1_LA00_CC_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_LA00_CC_N]
set_property PACKAGE_PIN AU39 [get_ports FMC1_LA01_CC_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_LA01_CC_P]
set_property PACKAGE_PIN AV39 [get_ports FMC1_LA01_CC_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_LA01_CC_N]
set_property PACKAGE_PIN AN38 [get_ports FMC1_LA02_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_LA02_P]
set_property PACKAGE_PIN AP38 [get_ports FMC1_LA02_N]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_LA02_N]
set_property PACKAGE_PIN AM41 [get_ports FMC1_LA03_P]
set_property IOSTANDARD LVCMOS18 [get_ports FMC1_LA03_P]
www.xilinx.com
Appendix C
for the latest XDC file.
51
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