Xadc - Xilinx Virtex-7 VC7203 User Manual

Chapter 1: VC7203 Board Features and Operation
Table 1-20: VITA 57.1 FMC1 HPC Connections at JA4 (Cont'd)

XADC

Callout 31,
7 series FPGAs provide an Analog Front End (XADC) block. The XADC block includes a
dual 12-bit, 1 MSPS Analog-to-Digital Convertor (ADC) and on-chip sensors. See 7 Series
FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital
Converter User Guide (UG480)
The VC7203 board provides two options for providing power (VCCADC) to the analog
circuitry in the XADC. Either option can be selected by placing a shunt in one of two
positions on the 3-pin VCCADC SELECT header, J141 (callout 31,
•
•
In addition, the VC7203 board provides two options for providing the reference voltage for
the analog-to-digital converter. Either option can be selected by placing a shunt in one of
two positions on the 3-pin VREF SEL header J142 (callout 31,
•
•
44
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U1 FPGA Pin
AR17
AU19
AV19
AT20
AT19
AV16
AW16
AT16
AU16
BB19
BB18
AR20
Figure 1-2.
[Ref 1]
Pins 1-2 (VCCAUX): In this configuration VCCADC is provided from VCCAUX
through a low pass filter network.
Pin 2-3 (REG): In this configuration VCCADC is provided by an onboard regulator,
U43 (Analog Devices P/N ADP123AUJZ-R7). The output voltage of the regulator
VCCADC can be adjusted using the potentiometer R233.
Pins 1-2 (REG): In this configuration the ADC reference voltage is provided by an
onboard, low-temperature coefficient 1.25V reference, U45 (Texas Instruments P/N
REF3012AIDBZT)
Pin 2-3 (AGND): In this configuration the VREFP on XADC is connected to analog
ground and the ADC uses an on-chip reference.
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Net Name
FMC3_LA28_N
FMC3_LA29_P
FMC3_LA29_N
FMC3_LA30_P
FMC3_LA30_N
FMC3_LA31_P
FMC3_LA31_N
FMC3_LA32_P
FMC3_LA32_N
FMC3_LA33_P
FMC3_LA33_N
FMC3_PRSNT_M2C_L
for details on the capabilities of the analog front end.
VC7203 GTX Transceiver Characterization Board
FMC Pin
H32
G30
G31
H34
H35
G33
G34
H37
H38
G36
G37
H2
Figure 1-2):
Figure 1-2):
UG957 (v1.3) October 17, 2014