Intel Quark D2000 Design Manual page 29

UART
 Baud rate configurability between 300 baud and 2M baud
 Maximum baud rate is limited by system clock frequency divided by 16.
 Supported baud rates: 300, 1200, 2400, 4800, 9600, 14400, 19200, 38400,
57600, 76800, 115200; multiples of 38.4 Kbps and multiples of 115.2 Kbps up
to 2M baud
 Auto Flow Control mode as specified in the 16750 Standard
 Hardware Flow Control
 Software Flow Control (when Hardware Flow Control is disabled)
 Hardware Handshake Interface to support DMA capability
 Interrupt Control

FIFO support with 16B TX and RX FIFOs
 Support of RS485
 Differential driver/receiver is external to the SoC.
 Driver enable (DE) and Receiver enable (RE) outputs are driven from the SoC to
control the differential driver/receiver.
 Fractional clock divider that ensures less than 2% frequency error for most
supported baud rates.
 Fraction resolution is 4 bits.
 Exception: 2.07% error for 1.391 Mbaud, 2.12% for 1.882 Mbaud and 2Mbaud,
2.53% error for 1.684 Mbaud.
 9-bit data transfer mode to support a multi-drop system where one master is
connected to multiple slaves in a system.
November 2016
Document Number: 333580-002EN
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Intel® Quark™ Microcontroller D2000
Platform Design Guide
29