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Analog-to-Digital Converter (ADC)
11.0
Analog-to-Digital Converter (ADC)
The SoC implements a Successive-Approximation (SAR) Analog-to-Digital Converter
(ADC), which can take 19 single-ended analog inputs for conversion. The ADC is
characterized to operate over the AVDD (1.8 to 3.6V) analog input range.
Analog signal traces in the SoC should be shielded completely to minimize noise
coupling and crosstalk between analog signals.
Figure 26. Analog Shielding Requirements
Example: Analog signal traces A, B and C are shielded "agnd" net with metal
layers/traces adjacent, above and below the signals. An "agnd" trace should be added
on top of signal C if there will be another signal route over it.
11.1
Features
The following is a list of the ADC features:
19:1 multiplexed single-ended analog input channels, 6 high-speed inputs and 13
low-speed inputs.
Selectable resolution among 12-, 10-, 8-, and 6-bit (12-bit at 2.28 MSps and 6- bit
at 4 MSps).
Maximum achievable sampling rate = (adc clock frequency) / (selres + 2).
ADC parameters:
Differential Non-Linearity (DNL) = +/- 1.0 LSB
Integral Non-Linearity (INL) = +/- 2.0 LSB
SINAD = 68 dBFS
Offset Error = +/- 2 LSB (calibration enabled), +/- 64 LSB (calibration disabled)
Latencies:
Power-up time of <= 10 us
1 conversion cycle = (resolution bits + 2) cycles
November 2016
Document Number: 333580-002EN
Intel® Quark™ Microcontroller D2000
Platform Design Guide
39
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