Figure 4. Single-Ended Microstrip Diagram - Intel Quark D2000 Design Manual

nominal trace width to meet those impedance targets, refer to the individual interface
section.
The following general stackup recommendations should be followed:
 Microstrip layers are assumed to be built from 1/2oz. foil, plated up nominally
another 1 oz.; however, the trace thickness range defined allows for significant
process variance around this nominal.
 Based on the Intel® Quark™ Microcontroller D2000 layout layers, 3/4 dual stripline
is assumed to be built from 1 oz. copper.
 All high-speed signals should reference solid planes over the length of their routing
and should not cross plane splits. Ground referencing is preferred.
 Reference plane stitching vias must be used in conjunction with high-speed signal
layer transitions that include a reference plane change. Refer to each signal group
section for more specification.
 The parameter values for internal and external traces are the final thickness and
width after the motherboard materials are laminated, conductors plated, and
etched. Intel uses these exact values to generate the associated electrical models
for simulation.

Figure 4. Single-Ended Microstrip Diagram

Intel® Quark™ Microcontroller D2000
Platform Design Guide
12
System Assumptions
November 2016
Document Number: 333580-002EN