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Subsystem Details
3.2
General Design Guideline Assumptions
The following assumptions pertain to all the subsystems discussed in this chapter.
Package length compensation is needed. The length values are tested and
measured as package-pin-to-package-pin.
The breakout and breakin minimum spacing ratio is 1:1 for all interfaces.
The trace width/intra-spacing for differential pairs and trace width for single-
ended signals depend on the impedance.
For analog signals, it is important to keep the analog ground return path clean of
digital noise to maintain a high signal-to-noise ratio.
For technical specifications (such as speeds, supported resolutions, and data rates),
refer to the Intel® Quark™ Microcontroller D2000 Datasheet.
1. Follow the general guidelines in this section, if a specific interface design guide is
Note:
not available.
2. All the routing guidelines in this document are simulated based on the CRB
stackup.
Table 4.
Good Layout Practices
Stitching Vias
Provide stitching vias for layer transitions
Break-In/Break-Out Regions
1. If desired trace width cannot be maintained in the break regions, maintain a minimum trace
width of 3.5 mil.
2. If desired trace spacing cannot be maintained in the break regions, maximize the trace
spacing.
Over and Around the Voids
1. Avoid routing over the voids and reference plane splits. Consult the SIE if split crossing
cannot be avoided
2. When going around the voids, maintain a minimum spacing of 1xh between signal trace and
void. Desirable spacing is 3xh where "h" is the distance to the nearest reference plane.
Lateral Distance to Reference Plane Edge
1. Keep a signal trace 4xh away from the edge of the reference plane.
November 2016
Document Number: 333580-002EN
§
Intel® Quark™ Microcontroller D2000
Platform Design Guide
19
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