Drive Strength Programmability Options - Intel i960 Design Manual

Intel® i960® RM/RN I/O Processor
®
Intel 80960RM/RN Processor Memory Subsystem
The drive strengths for the SDRAM signals are independently programmable using the SDCR
register. Table 4-4
programmed. The
Presence Detect EEROM (SPD) located on the DIMM. The I
processor
Table 4-4.

Drive Strength Programmability Options

Bus
Width
32
64
72
NOTES:
1. The Memory Size column is based on 16 Mbit SDRAM technology. If 64 Mbit SDRAM is populated, then the
size will increase appropriately. Each bank's technology may be programmed independently.
2. If one SDRAM bank is unpopulated, then the corresponding SCKE and SCE is unconnected.
Specific SDRAM signal topologies have been validated for 66 MHz operation.
Figure 4-9
should verify any other signal topologies.
To minimize crosstalk, SDRAM signal routing should use a minimum of 4 mils spacing and 4 mils
trace width. SDRAM clocks (out of the buffer) should use a minimum of 12 mils spacing and
6 mils trace width.
16
lists some example SDRAM configurations and how the SDCR should be
RM/RN I/O processor
with the SPD.
Memory
Form
1
Size Bank 0
Factor
(Mbytes)
4 2x1M16
8 4x2M8
On-board
8 4x1M16
16 8X2M8
8 1 4x1M16
Single-si
ded
16 8x2M8
DIMM
16 1 4x1M16
Double-si
ded
32 8x2M8
DIMM
4x1M16
16
2
32 4x1M16
Single-si
ded
24 8x2M8
DIMMs
32 8x2M8
16 On-board 9x2M8
1
Single-si
9x2M8
16
ded
DIMM
1
Double-si
32 9x2M8
ded
DIMM
2
Single-si
32 9x2M8
ded
DIMMs
illustrate the proven topologies and are recommended. Proper signal integrity analysis
determines the SDRAM configuration with the Serial
2
C bus interfaces the
SDCR[3] SDCR[4]
Bank 1
(DQ) (CKE0)
0 0
0 0
0 0
None
0 1
0 0
0 1
4x1M16 1 0
8x2M8 1 1
4x1M16 1 0
8x2M8 1 0
*
4x1M16 1 1
8x2M8 1 1
0 1
None
0 1
9x2M8 1 1
9x2M8 1 1
RM/RN I/O
SDCR[5] SDCR[6] SDCR[7]
(CKE1) (DQM) (SA[11:0])
2
0 0 0
2
0 0 0
2
0 0 0
2
0 0 1
2
0 0 0
2
0 0 1
0 1 1
1 1 1
0 1 1
1 1 1
0 1 1
1 1 1
2
0 0 1
2
0
0 1
1 1 1
1 1 1
Figure 4-5 through
Design Guide