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Clocking Guidelines; Layout Guidelines For Add-In Cards; Pci Add-In Card Example Configuration - Intel i960 Design Manual

Rm/rn i/o processor
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6.0

Clocking Guidelines

RM/RN I/O processor
primary PCI bus and the secondary PCI bus are referenced to the P_CLK input. The system must
provide clocks for any devices on the secondary PCI bus and ensure that system level goals for
clock skew and jitter are met.
6.1

Layout Guidelines for Add-in Cards

A PCI edge connector provides a singular PCI clock which must only be connected to one load on
the add-in card. Add-in cards which contain the
jitter clock driver/buffer to make multiple copies of the PCI clock for the
and any devices on the secondary PCI bus. See
widely available (typically from Cypress, Motorola, National Semiconductor, etc.)
The PCI bus specification allows a maximum PCI clock skew of 2 ns between any two devices
connected on the PCI bus. To minimize skew on the primary PCI bus, place the clock driver device
as close as possible to the PCI edge connector. Trace lengths from the PCI edge connector to the
clock driver ("A" in
input ("B" in
For the secondary PCI bus, allowable skew is 2 ns between the
input and any device on the secondary PCI bus. This allows the trace lengths from the clock driver
to the secondary PCI clock inputs ("C" and "D" in
RM/RN I/O processor
clock routes shorter than eight inches to provide a skew of less than 2 ns.
Figure 6-15. PCI Add-in Card Example Configuration
P_CLK
from Edge
Connector
NOTES:
1. Trace length between source component and resistor must be <1 inch.
2. All resistor values are 22 Ohms.
Design Guide
uses P_CLK (synchronous clock) input for clocking. All AC timings on the
Figure
6-15), and from the clock driver to the
Figure
6-15) must be as short as physically possible (max length 2.5 inches).
P_CLK input to accommodate layout. In general, keep these secondary
PLL Clock
Generator
See notes 1,2
A
PCLK0
PCLK1
PCLK2
Intel® i960® RM/RN I/O Processor
RM/RN I/O processor
Figure
6-15. Such clock driver/buffer devices are
RM/RN I/O processor
Figure
6-15) to be longer than the trace to the
*
Clocking Guidelines
should use a low skew, low
RM/RN I/O processor
RM/RN I/O processor
P_CLK
P_CLK
80960RM/RN
B
P_CLK
C
Secondary
PCI Device
D
Secondary
PCI Device
27

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