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Table F-1.
540-Lead H-PBGA Pinout — Intel
Ball #
AK1
AK2
AK3
AK4
AK5
AK6
AK7
AK8
AK9
AK10
AK11
AK12
AK13
AK14
AK15
AK16
AK17
AK18
AK19
AK20
AK21
AK22
AK23
AK24
AK25
AK26
AK27
AK28
AK29
AK30
AK31
AK32
Design Guide
Signal
Ball #
V
AL1
SS
V
AL2
CC
V
AL3
CC
V
AL4
SS
S_AD37/ N/C
AL5
S_AD40/ N/C
AL6
S_AD45/ N/C
AL7
S_AD48/ N/C
AL8
S_AD53/ N/C
AL9
S_AD56/ N/C
AL10
S_AD61/ N/C
AL11
S_PAR64/ N/C
AL12
S_REQ64#
N/C
AL13
/
S_AD01
AL14
S_AD06
AL15
V
AL16
SS
S_AD09
AL17
S_AD12
AL18
S_PAR
AL19
S_LOCK#
AL20
S_FRAME#
AL21
S_AD17
AL22
S_AD22
AL23
S_AD24
AL24
S_AD29
AL25
S_RST#
AL26
S_REQ2#
AL27
S_GNT3#
AL28
S_GNT5#
AL29
V
AL30
CC
V
AL31
CC
V
AL32
SS
Intel® i960® RM/RN I/O Processor
®
Intel
80960RM/RN Processor PBGA Signal Ball Map
®
®
i960
RM I/O Processor Processor (Sheet 5 of 5)
Signal
V
SS
V
CC
V
CC
V
CC
V
CC
N/C
V
CC
N/C
V
CC
N/C
V
CC
N/C
V
CC
S_AD02
V
CC
N/C
V
CC
S_AD13
*
V
CC
S_STOP#
V
CC
S_AD18
V
CC
S_AD25
V
CC
S_REQ0#
V
CC
S_REQ4#
V
CC
V
CC
V
CC
V
SS
Ball #
Signal
AM1
V
SS
AM2
V
SS
AM3
V
SS
AM4
V
CC
AM5
N/C
AM6
N/C
AM7
N/C
AM8
N/C
AM9
N/C
AM10
N/C
AM11
N/C
AM12
N/C
AM13
N/C
AM14
S_AD03
AM15
S_AD07
AM16
V
CC
AM17
S_AD10
AM18
S_AD14
AM19
S_SERR#
AM20
S_DEVSEL#
AM21
S_C/BE2#
AM22
S_AD19
AM23
S_AD23
AM24
S_AD26
AM25
S_AD30
AM26
S_GNT0#
AM27
S_GNT2#
AM28
S_GNT4#
AM29
V
SS
AM30
V
SS
AM31
V
SS
AM32
V
SS
97
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