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Table F-1.
540-Lead H-PBGA Pinout — Intel
Ball #
L1
L2
L3
L4
L5
L28
L29
L30
L31
L32
M1
M2
M3
M4
M5
M28
M29
M30
M31
M32
N1
N2
N3
N4
N5
N28
N29
N30
N31
N32
P1
P2
P3
P4
P5
P28
P29
P30
P31
Design Guide
Intel
®
Signal
Ball #
P_DEVSEL#
P32
P_TRDY#
R1
P_IRDY#
R2
V
R3
SS
P_FRAME#
R4
SDQM4
R5
SDQM0
R28
SCAS#
R29
V
R30
CC
SWE#
R31
P_SERR#
R32
V
T1
CC
P_PERR#
T2
P_LOCK#
T3
P_STOP#
T4
SCE1#
T5
V
T28
SS
SCE0#
T29
SDQM5
T30
SDQM1
T31
P_AD14
T32
P_AD15
U1
P_PAR
U2
V
U3
SS
P_C/BE1#
U4
SA02
U5
SA01
U28
SA00
U29
V
U30
CC
SRAS#
U31
P_AD10
U32
V
V1
CC
P_AD11
V2
P_AD12
V3
P_AD13
V4
SA06
V5
V
V28
SS
SA05
V29
SA04
V30
Intel® i960® RM/RN I/O Processor
®
80960RM/RN Processor PBGA Signal Ball Map
®
i960
RM I/O Processor Processor (Sheet 3 of 5)
Signal
SA03
P_AD07
P_C/BE0#
P_AD08
V
SS
P_AD09
SA10
SA09
SA08
V
CC
SA07
P_AD03
V
CC
P_AD04
P_AD05
P_AD06
SCKE0
V
*
SS
SBA1
SBA0
SA11
P_AD00
P_AD01
P_AD02
V
SS
P_REQ64#/ N/C
SDQM3
SDQM6
SDQM2
V
CC
SCKE1
N/C
V
CC
N/C
N/C
N/C
N/C
V
SS
SCB6
Ball #
Signal
V31
SCB2
V32
SDQM7
W1
P_AD62/ N/C
W2
P_AD63/ N/C
W3
P_PAR64/ N/C
W4
V
SS
W5
P_C/BE4#|| N/C
W28
DQ48
W29
DQ16
W30
SCB7
W31
V
CC
W32
SCB3
Y1
P_AD58/ N/C
Y2
V
CC
Y3
P_AD59/ N/C
Y4
P_AD60/ N/C
Y5
P_AD61/ N/C
Y28
DQ50
Y29
V
SS
Y30
DQ18
Y31
DQ49
Y32
DQ17
AA1
P_AD54/ N/C
AA2
P_AD55/ N/C
AA3
P_AD56/ N/C
AA4
V
SS
AA5
P_AD57/ N/C
AA28
DQ52
AA29
DQ20
AA30
DQ51
AA31
V
CC
AA32
DQ19
AB1
P_AD50/ N/C
AB2
V
CC
AB3
N/C
AB4
N/C
AB5
N/C
AB28
DQ54
AB29
V
SS
95
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