Table of Contents
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Contents
1.0
Introduction ................................................................................................................................... 9
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2.0
80960RM/RN Processor Ball Map...................................................................................... 9
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2.1
3.0
Routing Guidelines .....................................................................................................................11
3.1
Trace Length Limits .......................................................................................................11
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4.0
80960RM/RN Processor Memory Subsystem ..................................................................12
4.1
ROM, SRAM, or Flash Guidelines .................................................................................12
4.1.1
Layout Guidelines ..........................................................................................................13
4.1.2
Wait State Profiles .........................................................................................................13
4.2
SDRAM Guidelines........................................................................................................14
4.2.1
Layout Guidelines ..........................................................................................................15
4.2.2
SDRAM Clocking and Clock Buffer Specifications ........................................................20
4.2.3
SDRAM Power Failure Guidelines.................................................................................23
4.2.4
System Assumptions .....................................................................................................23
4.2.5
External Logic Required for Power Failure ....................................................................23
5.0
Interrupt Routing .........................................................................................................................25
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5.1
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5.2
6.0
Clocking Guidelines ....................................................................................................................27
6.1
Layout Guidelines for Add-in Cards...............................................................................27
6.2
Layout Guidelines for Motherboards..............................................................................28
6.3
Clock Vendors ...............................................................................................................29
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7.0
80960RM/RN Processor Signals Requiring Pull-Up/Down Resistors...............................30
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8.0
80960RM/RN Processor Signals Requiring Pull-Up/Down Resistors...............................32
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9.0
80960RM/RN Processor 5 V and 3.3 V Design Considerations .......................................34
9.1
Providing 3.3 V in a 5 V System ....................................................................................34
9.2
Choosing a Power Source .............................................................................................36
9.3
PCI Adapter Card Power Source...................................................................................37
9.4
V
9.5
V
CCPLL
9.6
Pullups and Pulldown Resistors ....................................................................................38
9.7
FAIL# .............................................................................................................................39
10.0
Processor Power Supply Decoupling .........................................................................................40
10.1
High Frequency Decoupling ..........................................................................................40
10.2
Bulk Decoupling Capacitance........................................................................................41
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11.0
80960RM/RN Processor Based Reference Design ..........................................................42
12.0
Debug Connector Recommendations.........................................................................................43
12.1
PBGA Sockets and Headers .........................................................................................43
12.2
Logic Analyzer Connectivity...........................................................................................45
Design Guide
80960RM/RN Processor PBGA Signal Ball Map .................................................10
80960RM/RN Processor Implementation on a MotherBoard...............................25
80960RM/RN Processor Implementation on an Add-in Card ..............................26
Pins Requirement..............................................................................................38
*
) .................................................................................37
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Intel
i960
RM/RN I/O Processor
3
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