Sdram Interface - Analog Devices ADSP-BF526 EZ-Board Manual

SDRAM Interface

Table 1-1. EZ-Board Internal Memory Map (Cont'd)
Start Address
0xFFA1 4000
0xFFA1 8000
0xFFA1 C000
0xFFA2 0000
0xFFA2 4000
0xFFB0 0000
0xFFB0 1000
0xFFC0 0000
0xFFE0 0000
Table 1-2. EZ-Board External Memory Map
Start Address
0x0000 0000
0x2000 0000
0x2010 0000
0x2020 0000
0x2030 0000
0x2040 0000
SDRAM Interface
The ADSP-BF526 processor connects to a 64 MB Micron
MT48H32M16-75 chip through the external bus interface unit (EBIU).
The SDRAM chip can operate at a maximum clock frequency of 80 MHz,
which is the ADSP-BF526 processor limitation when operating VDDEXT
at 1.8V.
With a CCES or VisualDSP++ session running and connected to the
EZ-Board via the USB standalone debug agent, the SDRAM registers are
1-16
Content
Reserved
L1 SCRATCHPAD SRAM (4K BYTE)
Reserved
SYSTEM MMR REGISTERS
CORE MMR REGISTERS
End Address
0x03FF FFFF
0x200F FFFF
0x201F FFFF
0x202F FFFF
0x203F FFFF
0xEEFF FFFF
ADSP-BF526 EZ-Board Evaluation System Manual
Content
SDRAM bank 0 (SDRAM)
ASYNC memory bank 0 (flash)
ASYNC memory bank 1 (flash)
ASYNC memory bank 2 (flash)
ASYNC memory bank 3 (flash)
Reserved