Sdram Interface - Analog Devices ADSP-21479 EZ-Board Manual

SDRAM Interface

Table 1-2. EZ-Board External (Interface-Accessible) Memory Map
Start Address
0x0020 0000
0x0400 0000
0x0800 0000
0x0C00 0000
0x0C00 0000
0x0C00 0000
SDRAM Interface
The ADSP-21479 processor connects to a 32 MB Micron
MT48LC16M16A2P-6A chip through the SDRAM controller. The
SDRAM memory controller on the processor and SDRAM memory chip
are powered by the on-board 3.3V regulator. The SDRAM controller and
memory on the EZ-Board can operate at a maximum clock frequency of
133 MHz.
With a CCES or VisualDSP++ session running and connected to the
EZ-Board via the USB standalone debug agent, the SDRAM registers are
configured automatically each time the processor is reset. The values are
used whenever SDRAM is accessed through the debugger (for example,
when viewing memory windows or loading a program).
To disable the automatic setting of the SDRAM registers, do one of the
following:
• CCES users, choose Target > Settings > Target Options and clear
the Use XML reset values check box.
• VisualDSP++ users, choose Settings > Target Options and clear
the Use XML reset values check box.
1-14
End Address Content
0x009F FFFF SDRAM (
0x043F FFFF Flash memory (
0x08FF FFFF Unused chip select (
0x0BFF FFFF Unused chip select (
0x0C0F FFFF SRAM (
0x0C07 FFFF SRAM (
ADSP-21479 EZ-Board Evaluation System Manual
)
MS0
)
MS1
) for non-SDRAM addresses
MS2
) for SDRAM addresses
MS2
) for 16-bit address space
MS3
) for 32-bit address space
MS3