Sdram Interface - Analog Devices ADSP-BF518F EZ-Board Manual

Table 1-2. EZ-Board External Memory Map (Cont'd)
Start Address
0x2010 0000
0x2020 0000
0x2030 0000
0x2040 0000

SDRAM Interface

The ADSP-BF518F processor connects to a 64 MB Micron
MT48LC32M16A2TG-75 chip through the external bus interface unit
(EBIU). The SDRAM chip can operate at a maximum clock frequency of
80 MHz, which is the ADSP-BF518F processor limitation.
With a CCES or VisualDSP++ session running and connected to the
EZ-Board via the USB standalone debug agent, the SDRAM registers are
configured automatically each time the processor is reset. The values are
used whenever SDRAM is accessed through the debugger (for example,
when viewing memory windows or loading a program).
To disable the automatic setting of the SDRAM registers, do one of the
following:
• CCES users, choose Target > Settings > Target Options and clear
the Use XML reset values check box.
• VisualDSP++ users, choose Settings > Target Options and clear
the Use XML reset values check box.
For more information on changing the reset values, refer to the online
help.
An example program is included in the EZ-Board installation directory to
demonstrate how to setup and access the SDRAM interface. For more
ADSP-BF518F EZ-Board Evaluation System Manual
Using the ADSP-BF518F EZ-Board
End Address
0x201F FFFF
0x202F FFFF
0x203F FFFF
0xEEFF FFFF
Content
ASYNC memory bank 1 (flash)
ASYNC memory bank 2 (flash)
ASYNC memory bank 3 (flash)
Reserved
1-15