Sdram Interface - Analog Devices Lite ADSP-BF538F EZ-KIT System Manual

SDRAM Interface

SDRAM Interface
1-8
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Table 1-1. EZ-KIT Lite Evaluation Board Memory Map
Start Address End Address
External
0x0000 0000 0x03FF FFFF
Memory
0x2000 0000 0x200F FFFF
0x2010 0000 0x201F FFFF
0x2020 0000 0x202F FFFF
0x2030 0000 0x203F FFFF
All other locations
Internal
0xFF80 0000 0xFF80 3FFF
Memory
0xFF80 4000 0xFF80 7FFF
0xFF90 0000 0xFF90 7FFF
0xFF90 4000 0xFF90 7FFF
0xFFA0 0000 0xFFA0 7FFF
0xFFA1 0000 0xFFA1 3FFF
0xFFA0 8000 0xFFA0 BFFF
0xFFB0 0000 0xFFB0 0FFF
0xFFC0 0000 0xFFDF FFFF
0xFFE0 0000 0xFFFF FFFF
All other locations
The three SDRAM control registers must be initialized in order to use the
MT48LC32M8A2 32M x 16 bits (64 MB) SDRAM memory. When you
are in a VisualDSP++ session and connect to the EZ-KIT Lite board, the
ADSP-BF538F EZ-KIT Lite Evaluation System Manual
Content
SDRAM bank 0 (SDRAM). See
face" on page 1-8.
ASYNC memory bank 0. See "Flash Memory" on
page 1-10.
ASYNC memory bank 1. See "Flash Memory" on
page 1-10.
ASYNC memory bank 2. See "Flash Memory" on
page 1-10.
ASYNC memory bank 3. See "Flash Memory" on
page 1-10.
Not used
Data bank A SRAM 16 KB
Data bank A SRAM/CACHE 16 KB
Data bank B SRAM 16 KB
Data bank B SRAM/CACHE 16 KB
Instruction bank A SRAM 32 KB
Instruction bank B SRAM 16 KB
Instruction SRAM/CACHE 16 KB
Scratch pad SRAM 4 KB
System MMRs 2 MB
Core MMRs 2 MB
Reserved
"SDRAM Inter-