Programmable Flags - Analog Devices ADSP-BF526 EZ-Board Manual

digipot, which is configurable over the 2-wire interface (TWI) signals.
Refer to the power-on-self test (POST) example in the ADSP-BF526
installation directory for information on how to set up the TWI interface.
The core voltage and clock rate can be set on the fly by the processor. The
input clock is 25 MHz. A 32.768 kHz crystal supplies the real-time clock
(RTC) inputs of the processor. The default boot mode for the processor is
external parallel flash boot. See
page 2-10 for information on how to change the default boot mode.

Programmable Flags

The processor has 50 general-purpose input/output (GPIO) signals spread
across four ports (
depend on the ADSP-BF526 processor setup. The following tables show
how the programmable flag pins are used on the EZ-Board.
• programmable flag pins in
PF
• programmable flag pins in
PG
• programmable flag pins in
PH
• programmable flag pins in
PJ
Table 2-1. PF Port Programmable Flag Connections
Processor Pin Other Processor Function
PF0 PPID0/DR0PRI/ND_D0A
PF1 PPID1/RFS0/ND_D1A
PF2 PPID2/RSCLK0/ND_D2
PF3 PPID3/DT0PRI/ND_D3A
ADSP-BF526 EZ-Board Evaluation System Manual
ADSP-BF526 EZ-Board Hardware Reference
"Boot Mode Select Switch (SW1)" on
, , , and ). The pins are multi-functional and
PF PG PH PJ
EZ-Board Function
Default:
Land grid array via
Default:
Land grid array via
Default:
Land grid array via
Default:
Land grid array via
Table 2-1
Table 2-2
Table 2-3
Table 2-4
on
PPID0 P3.18
.
P7.A
on
PPID1 P3.17
.
P7.A2
on
PPID2 P3.20
.
P7.A4
on
PPID3 P3.19
.
P7.A5
via .
RN1
via .
RN1
via .
RN1
via .
RN1
2-3