Sdram Interface; Parallel Flash Memory Interface - Analog Devices EZ-Board ADSP-BF518F Manual

SDRAM Interface

The ADSP-BF518F processor connects to a 64 MB Micron
MT48LC32M16A2TG-75 chip through the external bus interface unit
(EBIU). The SDRAM chip can operate at a maximum clock frequency of
80 MHz, which is the ADSP-BF518F processor limitation.
With a VisualDSP++ session running and connected to the EZ-Board via
the USB standalone debug agent, the SDRAM registers are configured
automatically each time the processor is reset. The values are used when-
ever SDRAM is accessed through the debugger (for example, when
viewing memory windows or loading a program).
To disable the automatic setting of the SDRAM registers, select Target
Options from the Settings menu in VisualDSP++ and uncheck Use XML
reset values. For more information on changing the reset values, refer to
the online Help.
An example program is included in the EZ-Board installation directory to
demonstrate how to setup and access the SDRAM interface. For more
information on how to initialize the registers after a reset, search the Visu-
alDSP++ online Help for "reset values".

Parallel Flash Memory Interface

The parallel flash memory interface of the ADSP-BF518F EZ-Board con-
tains a 4 MB (2M x 16 bits) Numonyx M29W320EB chip. Flash memory
connects to the 16-bit data bus and address lines 1 through 19. Chip
enable is decoded by the
gates. The address range for flash memory is
ADSP-BF518F EZ-Board Evaluation System Manual
Using ADSP-BF518F EZ-Board
select lines through NAND and AND
AMS0—3
to
0x2000 0000 0x203F FFFF
.
1-11