Analog Devices ADSP-BF526 EZ-Board Manual page 65

Table 2-2. PG Port Programmable Flag Connections
Processor Pin Other Processor Function
PG0 HWAIT
PG1 SPISS#/SPISEL1#
PG2 SPISCK
PG3 SPIMISO/DR0SECA
PG4 SPIMOSI/DT0SECA
PG5 TMR1/PPIFS2/TFS0A
PG6 DT0PRIA/TMR2/PPIFS3
PG7 TMR3/DR0PRIA/UART0TX
PG8 TMR4/RFS0A/UART0RX/
TACI4
PG9 TMR5/RSCLK0A/TACI5
PG10 TMR6/TSCLK0A/TACI6
ADSP-BF526 EZ-Board Evaluation System Manual
ADSP-BF526 EZ-Board Hardware Reference
EZ-Board Function
Default:
UART1 CTS
P9.12
(
P2.37
Default: SPI flash (
Expansion interface II (
land grid array via
Default: SPI flash (
Expansion interface II (
via
P7.B9
Default: SPI flash (
Expansion interface II (
grid array via
Default: SPI flash (
Expansion interface II (
grid array via
Default:
Land grid array via
Default:
Expansion interface II (
via
P7.B18
Default:
Expansion interface II (
grid array via
Default:
Expansion interface II (
grid array via
Default:
Expansion interface II (
via
P7.B11
Default:
Expansion interface II
P7.B12
via and
PB1 SW21.1 RN5
( ) via ,
HWAIT U32 SW14.1
, GPIO , expansion interface II
CHG JP15.1
, , ), land grid array via
P4.37 J1.52
) CS via
U6
,
P2.21
.
P7.B26
).
U6
,
P2.24
.
) via
U6 RN3
,
P2.16
.
P7.B23
).
U6
,
P2.15
.
P7.B24
.
PPIFS2 P3.14
.
P7.B17
codec ( ) via
DT0PRIA U31
,
P2.13
.
codec ( ) via
DR0PRIA U31
,
P2.14
.
P7.B14
codec ( ) via
RFS0A U31
,
P3.35
.
P7.B15
codec ( ) via
RSCLK0A U31
,
P2.18
.
codec ( ) via
TSCLK0A U31
, land grid array via
P2.17
.
.
, host connector
.
P7.B27
and .
SW11.4 RN3
, , ),
P4.21 P4.26 P2.26
), land grid array
P4.24
.
, ), land
P2.27 P4.27
, ), land
P2.25 P4.25
.
SW7.2
), land grid array
P3.15
.
SW7.3
, ), land
P2.31 P3.36
.
SW7.4
, ), land
P2.20 P2.32
.
SW2.2
), land grid array
P3.38
.
SW2.1
2-5