Using The Sdram Interface; Table 3-1: Ez-Kit Lite Evaluation Board Memory Map - Analog Devices ADSP-21161N EZ-KIT LITE Manual

Table 3-1: EZ-KIT Lite Evaluation Board Memory Map

0x0000 0000
0x0002 0000
0x0002 8000
0x0004 0000
Internal
0x0005 0000
Memory
0x0008 0000
0x000A 0000
0x0010 0000
0x0020 0000
0x0400 0000
External
Memory
0x0800 0000
0x0C00 0000

3.4 Using the SDRAM Interface

In order to use the SDRAM memory the two SDRAM control registers need to be
set to the following values: SDRDIV = 0x1000 and SDCTL = 0x02014231
The SDCTL register configures the SDRAM controller for the following settings:
(1/2 CCLK, no SDRAM buffering option, 2 SDRAM banks, SDRAM mapped to
bank 0 only, no self-refresh, page size 256 words, SDRAM powerup mode is
prechrg, 8 CRB refs, and then mode reg set cmd, tRCD = 2 cycles, tRP=2 cycles,
tRAS=3 cycles, SDCL=1 cycle,
SDCLKE activated)
The SDRAM registers are configured automatically through the debugger.
Checking the appropriate box as shown in
allows manual configuration.
ADSP-21161N EZ-KIT Lite Evaluation System Manual
Start Address End Address
0x0001 FFFF
0x0002 1FFF
0x0002 9FFF
0x0004 3FFF
0x0005 3FFF
0x0008 7FFF
0x000A 7FFF
0x001F FFFF
0x002F FFFF
0x047F FFFF
0x0BFF FFFF
0x0FFF FFFF
IOP Registers (Internal)
Block 0 Long Word
Addressing
Block 1 Long Word
Addressing
Block 0 Normal Word
Addressing
Block 1 Normal Word
Addressing
Block 0 Short Word
Addressing
Block 1 Short Word
Addressing
Multi-processor
Memory Space
External Memory Space
Bank 0 (SDRAM)
External Memory Space
Bank 1 (FLASH)
External Memory Space
Bank 2
External Memory Space
Bank 3
and SDCLK0, SDCLK1, RAS, CAS and
Figure 3-1 disable this setting and
Content
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