Analog Devices ADSP-BF526 EZ-Board Manual page 66

Programmable Flags
Table 2-2. PG Port Programmable Flag Connections (Cont'd)
Processor Pin Other Processor Function
PG11 TMR7/HOST_WR#
PG12 DMAR1/UART1TXA/
HOST_ACK
PG13 DMAR0/UART1RXA/
HOST_ADDR/TACI2
PG14 TSCLK0A/MDC/HOST_RD#
PG15 TFS0A/MIIPHYINT#/
RMIIMDINT#/HOST_CE#
Table 2-3. PH Port Programmable Flag Connections
Processor Pin Other Processor Function
PH0 ND_D0/MIICRS/
RMIICRSDV/HOST_D0
PH1 ND_D1/ERXER/HOST_D1
PH2 ND_D2/MDIO/HOST_D2
PH3 ND_D3/ETXEN/HOST_D3
2-6
EZ-Board Function
Default:
GPIO
CHG
interface II (
grid array via
Default:
Power down PB via
connector
,
P2.39
Default:
OTP_FLAG_1P8V
host connector
,
P2.40
Default: host connector
PHY (
MDC
Default:
RMIIMDINT#
nector
array via
EZ-Board Function
Default: NAND data 0 (
carrier sense/receive data valid (
RMII
connector data 0 (
Default: NAND data 1 (
PHY receive error (
(
P9.29
Default: NAND data 2 (
PHY management bus
nector data 2 (
Default: NAND data 3 (
PHY transmit enable (
(
P9.25
ADSP-BF526 EZ-Board Evaluation System Manual
via and .
LED1 U3 RN5
, host connector
JP15.3
, ,
J1.51 P2.28 P2.38
.
P7.B6
via and .
LED2 U3 RN5
,
SW20.3 CHG
, expansion interface II (
P9.10
), land grid array via
P4.39
via and
PB2 SW21.2 RN5
via ,
SW20.5 USB_VRSEL
, expansion interface II (
P9.8
), land grid array via
P4.40
.
P9.2
) via , land grid array via
U29 SW12.2
codec ( ) via
TFS0A U31
PHY ( ), wake via
U29
, expansion interface II
P9.6
.
P7.B3
) via
U15
), land grid array via
P9.31
) via
U15
), host connector data 1
U29.21
), land grid array via
P6.B2
) via
U15
MDIO U29
), land grid array via
P9.27
) via
U15
), host connector data 3
U29.6
), land grid array via
P6.B5
, expansion
P9.4
, , ), land
P4.28 P4.38
GPIO , host
JP15.5
,
J1.54
.
P7.B8
.
via ,
SW20.6
,
J1.53
.
P7.B5
.
P7.B2
and
SW7.1 RN5
, host con-
SW20.4
, land grid
P2.19
.
RN4
), host
U29.36
.
P6.B3
.
RN4
.
RN4
via , host con-
SW12.1
.
P6.B6
.
RN4
.