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Description
Query Response
Example
Programming Commands
Common Commands
The event status enable register contains a mask value for the bits to be enabled in
the event status register. A bit set to one (1) in the event status enable register
enables the corresponding bit in the event status register to set the event summary
bit in the status byte register. A zero (0) disables the bit. Refer to the following table
for information about the event status enable register bits, bit weights, and what
each bit masks. The event status enable register is cleared at power-on. The *RST
and *CLS commands do not change the register. The *ESE? query returns the value
of the event status enable register.
Table 5-14. Event Status Enable Register
Bit
Bit Weight
a
7
128
6
64
5
32
4
16
3
8
2
4
1
2
0
1
a. A high enables the event status register bit.
<integer> is a mask from 0 to 255.
OUTPUT 720;"*ESE 32"
In this example, the *ESE 32 command enables CME (event summary bit) bit 5 of
the event status enable register. Therefore, when an incorrect programming com-
mand is received, the CME (command error bit) in the status byte register is set.
*ESR?
The *ESR (event status register) query returns the value of the event status register.
134
Enables
PON – Power On
Not Used
CME – Command Error
EXE – Execution Error
DDE – Device Dependent Error
QYE – Query Error
Not Used
OPC – Operation Complete
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