Processing Time; Bus Cycle Time - Mitsubishi Electric Melsec Q Series User Manual

3
SPECIFICATIONS

3.5 Processing Time

This section explains the bus cycle time and transmission delay time.

3.5.1 Bus cycle time

(1) When a single DP-Master is used
QJ71PB92V
Buffer memory
Internal buffer
DP-Slave 1
DP-Slave 2
DP-Slave 3
3
- 59 3.5 Processing Time
3.5.1 Bus cycle time
Treq(1) Tres(1)
Max_Tsdr(1)
Lr Pt(1) Tsdi(M)
MSI(Min. Slave Interval) *1
Total of Treq, Max_Tsdr and Tres *1
Figure 3.38 Bus Cycle Time (DP-Master: 1, DP-Slave: 3)
* 1 "MSI (Minimum polling cycle)" or "Total of Treq, Max_Tsdr and Tres", whichever is greater is Bc
(Bus cycle time). ( (1) (a) in this section)
* 2 If "MSI (Minimum polling cycle)" is greater than "Total of Treq, Max_Tsdr and Tres", the
QJ71PB92V transfers data from the internal buffer to the buffer memory within the "MSI (Minimum
polling cycle)".
Treq(2) Tres(2) Treq(3)
Max_Tsdr(2)
Pt(2) Tsdi(M)
Time
Tres(3)
Max_Tsdr(3)
Pt(3) Tsdi(M)
*2