Mitsubishi Electric Melsec Q Series User Manual page 261

7
PROGRAMMING
(2) Settings
(a) QJ71PB92V settings
(b) DP-Slave settings
FDL address
Transmission speed
Operation mode
I/O data area for FDL address 2
(Buffer memory)
I/O data area for FDL address 3
(Buffer memory)
* 1 Set the control master FDL address in the master parameter setting of GX Configurator-DP.
( (2) (c) in this section)
Set the standby master FDL address in the Intelligent function module switch setting of GX
Works2. ( (2) (d) in this section)
Table7.66 DP-Slave Settings (1st module)
FDL address
I/O data size
Table7.67 DP-Slave Settings (2nd module)
FDL address
I/O data size
7.9 Program Examples for Use in the Redundant System
7.9.1 I/O Data Exchange Program Examples
Table7.65 QJ71PB92V Settings
Item
Control master FDL address
Standby master FDL address
Input data area (for mode 3)
Output data area (for mode 3)
Input data area (for mode 3)
Output data area (for mode 3)
Item
Input data size
Output data size
Item
Input data size
Output data size
Description
*1
FDL address 0
*1
FDL address 1
1.5Mbps
Communication mode (mode 3)
6144 (1800 ) to 6239 (185F
H
14336 (3800 ) to 14431 (385F
H
6240 (1860 )
H
14332 (3860 )
H
Description
FDL address 2
96 words (192 bytes)
96 words (192 bytes)
Description
FDL address 3
1 words (2 bytes)
1 words (2 bytes)
1
2
3
)
H
)
H
4
5
6
7
8
7
- 72