Mitsubishi Electric Melsec Q Series User Manual page 57

3
SPECIFICATIONS
(12) Time control start request signal (Y19), Time control start response
signal (X19)
(a) Turn ON the Time control start request signal (Y19) when executing the time
(b) Turning ON the Time control start request signal (Y19) clears the information in
(c) The Time control start response signal (X19) turns ON when the time control over
(d) Read the execution result from the Time control setting response area
(e) Turning OFF the Time control start request signal (Y19) turns OFF the Time
Remark
(13) Communication READY signal (X1B)
(a) The Communication READY signal (X1B) turns ON when the Module READY
(b) The signal turns OFF when an error disabling I/O data exchange occurs on the
(c) Use the signal as an interlock signal for when turning ON the Data exchange start
(14) Module READY signal (X1D)
(a) This signal turns ON when the QJ71PB92V is started up. (This signal turns ON
(b) While the QJ71PB92V is not ready, this signal is OFF.
(15) Watchdog timer error signal (X1F)
(a) This signal turns ON when a watchdog timer error occurs on the QJ71PB92V.
(b) The Watchdog timer error signal (X1F) does not turn OFF until:
control over DP-Slaves according to the information set in the Time control setting
request area (Un\G26784 to Un\G26792).
the Time control setting response area (Un\G26800 to Un\G26812).
DP-Slaves is executed, and the execution result is stored in the Time control
setting response area (Un\G26800 to Un\G26812).
(Un\G26800 to Un\G26812), and turn OFF the Time control start request signal
(Y19).
control start response signal (X19).
For details on time control over DP-Slaves, refer to Section 4.3.1.
signal (X1D) turns ON and I/O data exchange is ready to be started. (The signal
turns ON only in the Communication mode (mode 3).)
QJ71PB92V.
request signal (Y00).
regardless of the operation mode.)
• The programmable controller is turned OFF and back ON again, or
• The QCPU is reset.
3.3 Input/Output Signals to/from Programmable Controller CPU
3.3.2 Details of I/O signals
1
2
3
4
5
6
7
8
3
- 16