Synthesizer - Tait TB8100 Service Manual

2.3.4

Synthesizer

TB8100 Service Manual
© Tait Electronics Limited September 2006
wide bandwidth. The appropriate filter is selected by software-controlled
PIN switches, according to the bandwidth selected in the Service Kit
(Configure > Base Station > Channel Profiles > General tab).
The IF amplifier is a two-transistor design with voltage and current
feedback, which provides sufficient gain to drive the digital receiver. The
16.9MHz signal is finally passed to the analogue-to-digital converter (ADC)
in the digital receiver via an anti-alias filter. This filter prevents IF noise at
frequencies above 16.9MHz, generated in the amplifier, from being sampled
by the ADC at other Nyquist zones.
The receiver synthesizer consists of a programmable frequency synthesizer
IC, the receiver VCO, and a stable known reference.
The synthesizer uses a phase-locked loop to lock the receiver VCO to a
stable known frequency reference. The synthesizer IC receives the divider
and control information from the RISC processor via a 3-wire serial bus
(clock, data and enable). When the data bits are latched in, the synthesizer
processes the incoming signals from the VCO feedback signal (f
the reference oscillator (f
The VCO feedback attenuator is a resistive divider that terminates the VCO
feedback signal in a fixed low impedance (50Ω). This attenuates the VCO
RF level down to a level suitable for the RF prescaler (within the synthesizer
IC).
A 12.8MHz temperature controlled crystal oscillator (TCXO) is used as the
internal reference oscillator. When the TCXO is active, the receiver
synthesizer is locked to an "internal reference mode" (by default).
Alternatively, a phase-locked 12.8MHz voltage controlled crystal oscillator
(VCXO) can be used as the external reference oscillator. When the VCXO
is active, the receiver synthesizer is locked to an "external reference mode".
In operation only one oscillator is active at any given time. Refer to
"Reference Switch" on page 35
external reference oscillator.
The reference oscillators are buffered, branched, and divided down to the
3.125kHz (default) or 2.5kHz divider reference within the synthesizer IC.
The same divider reference is maintained by dividing the VCO feedback
signal using the prescaler and programmable dividers of the synthesizer IC.
Phase lock is achieved when both divider references have the same phase and
frequency content (i.e. their difference is zero or DC). This is achieved by
the phase detector (part of the synthesizer IC), which compares both divider
references and delivers an error signal. A ±4mA charge pump circuit (also
part of the synthesizer IC) and the active loop filter circuit convert this error
signal to a DC voltage (0 to 22V
1. The normal lock range is between 3V and 16V.
).
ref
for details on the phase-locked 12.8MHz
1
) to tune the VCO for correction. The
Reciter Circuit Description
) and
vcofb
39