Rf Prober Interconnect; Piv-A Interconnect Assembly Procedure - Keithley 4200-SCS User Manual

Semiconductor characterization system
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Model 4200-SCS User's Manual
Figure 3-31
Schematic diagram of the PRB-C adapter cable
These SMA to SSMC Y adapter cables are appropriate for on-wafer pulse IV
testing of nominally DC structures.
RBTs to DC probes for a DC layout DUT structure, using the PRB-C Y adapter
cable.
These Y cables are not appropriate for higher frequency devices. The upper
frequency limit is not specified, because the effect of actual device layout and
probe configuration can have a significant impact. In general, any device that has
an F
scheme and the PRB-C cables.

RF Prober Interconnect

If the device has an RF layout (G-S-G), the Y adapter cables and DC probe
manipulators will most likely be insufficient. In the case of RF G-S-G pad layout,
do not use the 4200-PRB-C Y cables use the shorter SMA cables (6 in./15 cm)
supplied with the PIV-A package to connect directly from the RBTs to the RF
manipulators. The RBT with the power divider is connected to the Gate.
For additional information see the documentation included with the 4200-PRB-C
(PA-928).

PIV-A interconnect assembly procedure

1.
2.
4200-900-01 Rev. K / February 2017
much above 1GHz might oscillate when using a DC probe connection
T
Using the
Supplied interconnect parts on page 3-30
to
Figure
3-25,
Figure 3-26
the supplied torque wrench for the SMA connections on the RBTs, power divider and
manipulators. Use care when installing the cable to the scope card trigger SMB connector.
Perform one of the following procedures to connect the test system to the DUT:
• For DC structures, prepare the probe connection by disconnecting all DC cables from the
SSMC connectors on the needle holders. Continue setup of PIV-A by connecting a PRB-
C cable to the 15cm (6in) SMA cable attached to each RBT. Refer to
forget to connect the black shield jumpers to each other as shown in the middle of
3-32. Connecting shields together is necessary and very important, as it greatly reduces
the inductance that is caused by the loop area of the interconnect.
Return to
Section 3: Common Device Characterization Tests
Figure 3-32
and
Figure 3-27
to configure the test setup for PIV testing. Use
Section Topics
shows Pulse IV connections from
and
Supplied tools on page
Figure
3-31, refer
3-32. Don't
Figure
3-35

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