Mitsubishi Q01CPU User Manual page 671

Melsec-q series, qcpu
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12
TROUBLESHOOTING
Special
ACPU
Special
Register
Special
Register for
after
Register
Modification
Conversion
D9100
SD1100
D9101
SD1101
D9102
SD1102
D9103
SD1103
D9104
SD1104
D9105
SD1105
D9106
SD1106
D9107
SD1107
D9108
SD1108
D9109
SD1109
D9110
SD1110
D9111
SD1111
D9112
SD1112
D9113
SD1113
D9114
SD1114
D9116
SD1116
D9117
SD1117
D9118
SD1118
D9119
SD1119
D9120
SD1120
D9121
SD1121
D9122
SD1122
D9123
SD1123
D9124
SD1124
SD63
Table12.54 Special register
Name
Meaning
Bit pattern in units of
Fuse blown
16 points, indicating
module
the modules whose
fuses have blown
Step transfer
Timer setting valve
monitoring timer
and the F number at
setting
time out
Bit pattern, in units of
I/O module
16 points, indicating
verification error
the modules with
verification errors.
Number of
Number of annuciator
annuciator
detections
detections
Details
• Output module numbers (in units of 16 points), of which fuses have
blown, are entered in bit pattern. (Preset output module numbers
when parameter setting has been performed.)
b15 b14b13b12b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
1
1
0
0
0
0
0
0
0
SD1100
(YC0)
(Y80)
0
0
0
0
0
0
0
0
0
SD1101
1
0
0
0
0
0
0
0
0
SD1107
Y7
B0
Indicates fuse blow.
• Fuse blow check is executed also to the output module of remote I/
O station.
(If normal status is restored, clear is not performed. Therefore, it is
required to perform clear by user program.)
• Set the value of the step transition monitoring timer and the
annunciator number (F number) that will be turned ON when the
monitoring timer times out.
b15
to
b8
b7
to
F number setting
Timer time limit setting
(02 to 255)
(1 to 255 s:(1 s units))
• By turning ON any of SM1108 to SM1114, the monitoring timer
starts. If the transition condition following a step which corresponds
to the timer is not established within set time, set annunciator (F) is
turned on.)
• When I/O modules, of which data are different from those entered
at power-ON, have been detected, the I/O module numbers (in
units of 16 points) are entered in bit pattern. (Preset I/O module
numbers set in parmeters when parameter setting has been
performed.)
b15 b14b13b12b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
0
0
0
0
0
0
SD1116
1
0
0
0
0
0
0
0
0
SD1117
XY
190
1
0
0
0
0
0
0
0
0
SD1123
XY
7B0
Indicates an I/O module verify error.
• I/O module verify check is executed also to remote I/O station
modules.
(If normal status is restored, clear is not performed. Therefore, it is
required to perform clear by user program.)
• When one of F0 to 255 (F0 to 2047 for AuA and AnU) is turned on
by
1 is added to the contents of SD63. When
SET F
instruction is executed, 1 is subtracted from the contents
LEDR
of SD63.
(If the INDICATOR RESET switch is provided to the CPU module,
pressing the switch can execute the same processing.)
• Quantity, which has been turned on by
SD63 in BIN code. The value of SD63 is maximum 8.
12.8 Special Register List
Corresponding
CPU
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Y7
30
b0
QnA
Qn(H)
QnPH
1
0
0
0
0
0
0
XY
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
or
RST F
is stored into
SET F
12
- 347
9
10
11
12

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