Mitsubishi Q01CPU User Manual page 661

12
TROUBLESHOOTING
Number Name Meaning
b0 to b14:
0: Do not
refresh
1: Refresh
Refresh
b15 bit
processing
0: communication
selection when
SD778 with peripheral
the COM
device is
instruction is
executed
executed
1: communication
with peripheral
device is
nonexecuted
Remaining No.
of simultaneous
execution of
SD780 0 to 32
CC-Link
dedicated
instruction
SD781 Mask pattern of
to IMASK Mask pattern
SD793 instruction
SD781 Mask pattern of
to IMASK Mask pattern
SD785 instruction
SD794 PID limit setting
0: With limit
to (for incomplete
1: Without limit
SD795 derivative)
PID limit setting
0: With limit
SD794 (for incomplete
1: Without limit
derivative)
*9: Function version is B or later.
*13: The module whose first 5 digits of serial No. is 09012 or later.
Table12.51 Special register
Explanation
• Selects whether or not the data is refreshed when the COM instruction is
executed.
• Designation of SD778 is made valid when SM775 turns ON.
b15 b14 to b6 b5 b4 b3 b2
SD778
0
0/1 0/1 0/1 0/1 0/1
• Stores the remaining number of simultaneous execution of the CC-Link
dedicated instructions.
• Stores the mask patterns masked by the IMASK instruction as follows:
b15
l63
SD781 to
SD782 l79 to
to
l255
SD793 to
• Stores the mask patterns masked by the IMASK instruction as follows:
b15
l63
SD781 to
SD782 l79 to
to to
SD785 l127 to
• Specify the limit of each PID loop as shown below.
b15
SD794 Loop16 to
SD795 Loop32
to
• Specify the limit of each PID loop as shown below.
b15 to b8 b7
Loop8
SD794
Set by
(When Set)
b1 b0
0/1 0/1
I/O refresh
CC-Link refresh
Refresh of
MELSECNET/H and
MELSECNET/G
Automatic refresh of
intelligent function
U
modules
Auto refresh using
QCPU standard area of
multiple CPU system and
reading input/output from
group outside.
Auto refresh using the
multiple CPU high speed
transmission area of
multiple CPU system
Execution/non-
execution of
communication with
CPU module
U
b1 b0
l49
l48
S (During
l65 l64
execution)
l241
l240
b1 b0
l49
l48
S (During
l65 l64
execution)
l113 l112
b1 b0
U
Loop2 Loop1
Loop18 Loop17
b1 b0
U
Loop2 Loop1
to
12.8 Special Register List
Corres-
ponding
Corresponding
ACPU
CPU
D9
New QnU
New QnA
Qn(H)
QnPH
New
QnPRH
QnU
New Q00J/Q00/Q01
*13
Qn(H)
New
QnPRH
QnU
*9
New
Q00J/Q00/Q01
12
- 337
9
10
11
12