Mitsubishi Q01CPU User Manual page 670

12
TROUBLESHOOTING
Special
ACPU Special
Register
Special Register for
after
Register Modification
Conversion
D9053 SD1053
D9054 SD1054
D9055 SD1055 SD812
D9060 SD1060 SD392
D9072 SD1072
D9081 SD1081 SD714
D9085 SD1085
D9090 SD1090
D9091 SD1091
D9094 SD1094 SD251
D9095 SD1095 SD200
12
- 346 12.8 Special Register List
Table12.54 Special register
Name Meaning
Transition condition
Error transition number where error
occurred
Sequence step
Error sequence
number where error
step
occurred
Status latch
execution step Status latch step
number
Software Software version of
version internal software
Programmable
Data check of serial
controller
communication
communication
module
check
Number of Number of empty
empty blocks in blocks in
communications communications
request request registration
registrtion area area
Register for
setting time 1 s to 65535 s
check value
Number of
Number of special
special
functions modules
functions
over
modules over
Detailed error Self-diagnosis
code detailed error code
Head I/O
Head I/O number of I/
number of I/O
O module to be
module to be
replaced
replaced
DIP switch DIP switch
information information
Details
• Stores the transition condition number, where error code 84 occurred
in an SFC program, in BIN value.
Stores "0" when error code 80, 81, 82 or 83 occurred.
• Stores the sequence step number of transfer condition and
operation output in which error 84 occurred in the SFC program in
BIN code.
• Stores the step number when status latch is executed.
• Stores the step number in a binary value if status latch is executed
in a main sequence program.
• Stores the block number and the step number if status latch is
executed in a SFC program.
Block No.
(BIN)
Upper 8 bits
• Stores the software version of the internal system in ASCII code.
Stored into lower
Upper byte Lower byte
byte
Undefind value in
higher byte
For version "A", for example, "41
Note: The software version of the initial system may differ from the
version indicated by the version information printed on the rear
of the case.
• In the self-loopback test of the serial communication module, the
serial communication module writes/reads data automatically to
make communication checks.
• Stores the number of empty blocks in the communication request
registration area to the remote terminal module connected to the
MELSECNET/MINI-S3 master unit, A2CCPU or A52GCPU.
• Sets the time check time of the data link instructions (ZNRD,
ZNWR) for the MELSECNET/10.
• Setting range : 1 s to 65535 s (1 to 65535)
• Setting unit : 1 s
• Default value : 10 s (If 0 has been set, default 10 s is applied)
• For details, refer to the manual of each microcomputer program
package.
• Stores the detail code of cause of an instruction error.
• Stores the first two digits of the head I/O number of the I/O module,
which will be dismounted/mounted online (with power on), in BIN
value.
Example) Input module X2F0 H2F
• The DIP switch information of the CPU module is stored in the
following format.
0: OFF
1: ON
b15 to b5 b4 b3
D9095 0
Corresponding
Step No.
(BIN)
Lower 8 bits
" is stored.
H
b2 b1 b0
SW1
SW2
SW3
SW4
SW5
CPU
QnA
Qn(H)
QnPH
QnA
QnA
Qn(H)
QnPH
QnA
QnA
Qn(H)
QnPH
Qn(H)
QnPH