Xilinx HDMI 1.4 Product Manual page 97

4. For each Video PHY Controller instance, the above data structure needs to be initialized
based on its hardware configuration, which is passed through meta-structure from
xparameters.h uniquely identified by device ID.
To initialize the Video PHY Controller, call the following two API functions:
XVphy_Config *XVphy_LookupConfig(u16 DeviceId);
u32 XVphy_HdmiInitialize(XVphy *InstancePtr,
The Device ID can be found in xparameters.h:
XPAR_[Video PHY Controller Instance Name in IPI]_DEVICE_ID
Similarly, SystemFrequency is the system frequency, which can also be found in
xparameters.h
Note:
• Xilinx recommends initializing the Video PHY controller after the HDMI 1.4/2.0
Transmitter Subsystem initialization is completed.
• Registering the Video PHY Controller interrupts are part of system application
integration. Steps are shown in the previous section and not repeated here.
Interrupts
All interrupts generated by the HDMI 1.4/2.0 Transmitter Subsystem are listed here:
1. HPD – Peripheral I/O to detect HDMI cable 5.0V signal
a. Rising edge – Cable connected
b. Falling edge – Cable disconnected
2. Link Ready – Every time when Video PHY Controller is reconfigured, the link_clk is
regenerated. An HDMI TX sub-core register bit (link status bit) reflects the change of
link_clk status. When stable link_clk is detected, it is set to 1. When link_clk
becomes unstable, it is set to 0. The Link Ready is an interrupt to detect the change of
the link status bit.
a. Rising edge – Link is up
b. Falling edge – Link is down
3. Vertical Sync – This is to reflect the change of HDMI TX sub-core vsync input signal in
its video interface bus.
a. Rising edge – Vertical Sync is detected
4. HDCP 1.4 Interrupt (only available when HDCP 1.4 is enabled in hardware)
HDMI 1.4/2.0 TX Subsystem
PG235 October 4, 2017
Appendix C: Application Software Development
u8 QuadId,
XVphy_Config *CfgPtr,
u32 SystemFrequency);
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