Xilinx HDMI 1.4 Product Manual page 56

Table 4‐1: Vivado IDE Parameter to User Parameter Relationship (Cont'd)
Vivado IDE Parameter/Value
FIFO Depth
Design Topology
Pass-Through
Tx Only
TX PLL Type
CPLL
QPLL(GTXE2)
QPLL01(GTHE3/4)
RX PLL Type
CPLL
QPLL(GTXE2)
QPLL01(GTHE3/4)
Include NIDRU
Include (Tick)
Exclude (Untick)
Output Generation
For details, see the Vivado Design Suite User Guide: Designing with IP (UG896)
HDMI 1.4/2.0 TX Subsystem
PG235 October 4, 2017
C_ADDR_WIDTH
32
1024
2048
4096
8192
Example Design
C_EXDES_TOPOLOGY
C_EXDES_TX_PLL_SELECTION
C_EXDES_RX_PLL_SELECTION
C_EXDES_NIDRU
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Chapter 4:
User Parameter/Value
32
1024
2048
4096
8192
0
1
0
3
6
0
3
6
true
false
Design Flow Steps
Default Value
1024
0
0 (GTXE2)
6 (GTHE3/4)
3 (GTXE2)
0 (GTHE3/4)
true
[Ref 16].
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