Xilinx HDMI 1.4 Product Manual page 31

HDMI Link Output Interface
Table 2-6 shows the HDMI Link Output interface signals. This interface runs at the
link_clk clock rate.
Table 2‐6: HDMI Link Output Interface
Name
link_clk
LINK_DATA0_OUT_tdata
LINK_DATA0_OUT_tvalid
LINK_DATA1_OUT_tdata
LINK_DATA1_OUT_tvalid
LINK_DATA2_OUT_tdata
LINK_DATA2_OUT_tvalid
Data Display Channel Interface
Table 2-7 shows the Data Display Channel interface signals.
Table 2‐7: Data Display Channel (DDC) Interface
Name
ddc_scl_i
ddc_scl_o
ddc_scl_t
ddc_sda_i
ddc_sda_o
ddc_sda_t
HDCP 1.4 Key Input Interface (AXI4-Stream Slave Interface)
Table 2-8 shows the signals for HDCP 1.4 key interface. This interface runs at the
hdcp14_key_aclk (which is running at AXI4 Lite Clock).
Table 2‐8: HDCP 1.4 Key Input Interface
Name
HDCP_KEY_IN_tdata
HDCP_KEY_IN_tlast
HDCP_KEY_IN_tready
HDCP_KEY_IN_tuser
HDCP_KEY_IN_tvalid
HDMI 1.4/2.0 TX Subsystem
PG235 October 4, 2017
Direction Width
Input 1
Output 40
Output 1
Output 40
Output 1
Output 40
Output 1
Direction Width
Input 1
Output 1
Output 1
Input 1
Output 1
Output 1
Direction Width
Input 64
Input 1
Output 1
Input 8
Input 1
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Chapter 2: Product Specification
Description
Link clock
Link data 0
Link Data 0 Valid
Link data 1
Link Data 1 Valid
Link data 2
Link Data 2 Valid
Description
DDC serial clock in
DDC serial clock out
DDC serial clock tri-state
DDC serial data in
DDC serial data out
DDC serial data tri-state
Description
HDCP 1.4 key data
End of key data
Ready
Start of key data
Valid
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