Xilinx HDMI 1.4 Product Manual page 29

Table 2‐3: Native Video InputInterface (Cont'd)
Name
VIDEO_IN_vsync
Notes:
1. When native video interface is selected, s_axis_video_aclk and s_axis_video_aresetn are removed from the HDMI
1.4/2.0 Transmitter Subsystem interface ports.
2. video_clk is generated by Video PHY Controller LogiCORE IP Product Guide (PG230)
3. When native video interface is selected, there is no hardware reset.
4. You must provide the correct video timing information. You can choose to use Xilinx Video Timing Controller (vtc)
or design your own vtc module to generate the timing control signals for native video interface.
Audio Input Stream Interface
Table 2-4 shows the signals for AXI4-Stream audio input streaming interfaces. The audio
interface transports 24-bits audio samples in the IEC 60958 format. A maximum of eight
channels are supported. The audio interface is a 32-bit AXI4-Stream slave interface and runs
at the s_axis_audio_aclk clock rate.
Table 2‐4: Audio Input Stream Interface
Name
s_axis_audio_aclk
s_axis_audio_aresetn
AUDIO_IN_tdata
AUDIO_IN_tid
AUDIO_IN_tready
AUDIO_IN_tvalid
Audio Clock Regeneration Interface
The audio clock regeneration (ACR) interface has a Cycle Time Stamp (CTS) parameter
vector and an Audio Clock Regeneration Value (N) parameter vector. Both vectors are 20
HDMI 1.4/2.0 TX Subsystem
PG235 October 4, 2017
Direction
(4)
Input
Direction
Input
Input
Input
Input
Output
Input
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Chapter 2: Product Specification
Width
1 Vertical sync
Width
Clock (The audio streaming clock must be
1 greater than or equal or greater than 128 times
the audio sample frequency)
1 Reset (Active-Low)
Data
[31] P (Parity)
[30] C (Channel status)
[29] U (User bit)
[28] V (Validity bit)
32
[27:4] Audio sample word
[3:0] Preamble code
4'b0001 Subframe 1/start of audio block
4'b0010 Subframe 1
4'b0011 Subframe 2
3 Channel ID
1 Ready
1 Valid
Description
[Ref 24].
Description
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