Clocking - Xilinx HDMI 1.4 Product Manual

each pixel twice. When the video is sent out by the HDMI 1.4/2.0 Transmitter Subsystem, it
is sent as two fields of 1440x240 @ 30Hz video.

Clocking

The S_AXI_CPU_IN, VIDEO_OUT, and AUDIO_OUT can be run at their own clock rate. The
HDMI link interfaces and native video interface also run at their own clock rate. Therefore,
five separate clock interfaces are provided called s_axi_cpu_aclk,
s_axis_video_aclk, s_axis_audio_aclk, link_clk, and video_clk respectively.
The audio streaming clock must be greater than or equal to 128 times the audio sample
frequency. Because audio clock regeneration is not part of the HDMI TX subsystem, you
must provide an audio clock to the application. This can be achieved by using an internal
PLL or external clock source.
The AXI4-Lite CPU clock must run at 100 Mhz.
IMPORTANT:
The HDMI clock structure is illustrated in
X-Ref Target - Figure 3-10
TMDS
clock
HDMI 1.4/2.0 TX Subsystem
PG235 October 4, 2017
Data rate
< 3.4 Gbps
*1
Data
clock
Data rate
>3.4 Gbps
*4
Figure 3‐10: HDMI Clocking Structure
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Chapter 3:
Figure 3-10 and Table
8 bpc
/1
10 bpc
/1.25
Pixel
clock
12 bpc
/1.5
16 bpc
/2
Link
/4
clock
Designing with the Subsystem
3-3.
Dual
/2
Video
clock
Quad
/4
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