Interface Debug - Xilinx HDMI 1.4 Product Manual

Table B‐1: System Flow and State Information
At system start-up
VPHY log
------
GT init start
GT init done
TX frequency event
TX timer event
TX MMCM reconfig done
QPLL reconfig done
GT TX reconfig start
GT TX reconfig done
TX MMCM lock
QPLL lock
TX reset done
TX alignment done
HDMI TX log
------
Initializing HDMI TX core....
Initializing VTC core....
Reset HDMI TX Subsystem....
TX cable is connected....
TX Stream is Down
TX Set Stream, with TMDS (32)
TX Audio Unmuted
TX Stream is Up

Interface Debug

AXI4-Lite Interfaces
Read from a register that does not have all 0s as a default to verify that the interface is
functional. Output s_axi_arready asserts when the read address is valid, and output
s_axi_rvalid asserts when the read data/response is valid. If the interface is
unresponsive, ensure that the following conditions are met:
• The s_axi_aclk and aclk inputs are connected and toggling.
• The interface is not being held in reset, and s_axi_areset is an active-Low reset.
HDMI 1.4/2.0 TX Subsystem
PG235 October 4, 2017
While changing video stream from UART Menu
VPHY log
------
TX frequency event
QPLL lost lock
TX frequency event
TX timer event
TX MMCM reconfig done
QPLL reconfig done
GT TX reconfig start
GT TX reconfig done
TX MMCM lock
QPLL lock
TX reset done
TX alignment done
HDMI TX log
------
TX Set Stream, with TMDS (128)
TX Stream is Down
TX Audio Unmuted
TX Stream is Up
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Appendix B: Debugging
85
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