Xilinx HDMI 1.4 Product Manual page 64

through a customized audio generation block. The two AXI streams eventually reach the
HDMI_TX_SS core, which converts the AXI video and audio streams back to an HDMI stream
before being transmitted by the VPHY Controller core as a high-speed serial data stream.
The transition minimized differential signaling (TMDS) clock from the HDMI In interface is
forwarded to the HDMI TX transceiver via the SI53xx clock generator in the HDMI 2.0 FMC
card or on-board HDMI 2.0 circuitry.
In TX only mode, the colorbar pattern is generated by the TPG in form of AXI video stream
and the low frequency audio is generated by the customized audio processing block in form
of AXI audio stream. The two streams are forwarded to the HDMI_TX_SS for HDMI stream
conversion then to the VPHY for transmission.
High-level control of the system is provided by a simplified embedded processor
subsystem containing I/O peripherals and processor support IP. A clock generator block
and a processor system reset block supply clock and reset signals for the system,
respectively. See
processor subsystems supported by HDMI Example Design flow.
X-Ref Target - Figure 5-5
microblaze_ss
Microblaze
Debug
Module
Processor
System Reset
Module
Clock Wizard
AXI interconnect (AXI lite)
audio_ss
Audio Pattern
Gen
HDMI 1.4/2.0 TX Subsystem
PG235 October 4, 2017
Figure 5-5 and Figure 5-6
LMB
LMB
MicroBlaze
Processor
tpg_ss
Clock Wizard HDMI ACR
Figure 5‐5: HDMI Reference Design Block Diagram (MicroBlaze)
www.xilinx.com
for a block diagrams of the three types of
LMB bram
controller
Block RAM
LMB bram
controller
LMB bram
controller
Block RAM
LMB bram
controller
AXI INTC
HDMI
Test Pattern
AXI GPIO Transmitter
Generator
Subsystem
Chapter 5: Example Design
FPGA IO FPGA IO
AXI UART
AXI IIC
(lite)
HDMI
Video PHY
Receiver
Controller
Subsystem
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